Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2007-11-27
2007-11-27
Lamarre, Guy (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C711S005000
Reexamination Certificate
active
10975661
ABSTRACT:
A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 0 to N−1 and reading the stored bit symbols from the memory. The device comprises a look-up table for providing a first variable m and a second variable J satisfying the equation N=2m×J; and an address generator for generating a read address depending on the first and second variables m and J provided from the look-up table. The read address is determined by 2m(K mod J)+BROm(K/J), where K (0≦K≦(N−1)) denotes a reading sequence, BROm(y) is the bit-reversed m-bit value of y and / is a function in which a quotient of K divided by d is obtained, the quotient being an integer.
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Chaudry Mujtaba K.
Lamarre Guy
Samsung Electronics Co,. Ltd.
The Farrell Law Firm
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