Method and apparatus for completely covering a wafer with a...

Details Method and apparatus for completely covering a wafer with a... Method and apparatus for completely covering a wafer with a...

2007-06-19

2007-06-19

Ho, Tu-Tu (Department: 2818)

Semiconductor device manufacturing: process

With measuring or testing

C438S780000, C257S048000, C257SE23179, C257SE21530

Reexamination Certificate

active

11160154

ABSTRACT:
A method and apparatus for determining the complete coverage of a passivating material on the final conductive interconnection of a wafer containing integrated circuits. A test structure with the dimensions of the final interconnections of the integrated circuits is formed during manufacture of the integrated circuits and used to determine complete coverage of the wafer by creating an opening in the passivating material at the test structure, the size of the opening being indicative of the complete coverage of the wafer.

REFERENCES:
patent: 6166808 (2000-12-01), Greve
patent: 6753972 (2004-06-01), Hirose et al.
patent: 6897079 (2005-05-01), Hirose et al.
patent: 2004/0070773 (2004-04-01), Hirose et al.
patent: 2004/0145747 (2004-07-01), Jasapara

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