Test circuit and circuit test method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S731000, C714S744000

Reexamination Certificate

active

11081619

ABSTRACT:
The test circuit tests a test target circuit and outputs a test result to a tester. The test circuit includes a first clock generator, a second clock generator, a test target circuit, a BIST circuit for performing the test, and a tester synchronous circuit. The BIST circuit repeats the test the number of times determined by the first clock and the second clock. The tester synchronous circuit selects a test result so as to output all the test results from the BIST circuit and outputs the selected test result.

REFERENCES:
patent: 5867453 (1999-02-01), Wang et al.
patent: 5875153 (1999-02-01), Hii et al.
patent: 6347056 (2002-02-01), Ledford et al.
patent: 6421789 (2002-07-01), Ooishi
patent: 6442722 (2002-08-01), Nadeau-Dostie et al.
patent: 6583642 (2003-06-01), Huang et al.
patent: 6760865 (2004-07-01), Ledford et al.
patent: 7000164 (2006-02-01), Siegel et al.
patent: 7114113 (2006-09-01), Yonaga et al.
patent: 2004-107412 (2002-04-01), None
patent: 2003-36694 (2003-02-01), None

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