Generating an abbreviated netlist including pseudopin inputs...

Details Generating an abbreviated netlist including pseudopin inputs... Generating an abbreviated netlist including pseudopin inputs...

2007-04-10

2007-04-10

Chase, Shelly (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10771775

ABSTRACT:
A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At least one pseudo input is defined to represent a portion of the nonproprietary circuit to emulate the nonproprietary circuit output. An output node of the embedded vendor circuit to which an input of the customer designed circuit is connectable is identified. A test netlist is created which represents circuitry that produces output states at the output node which would be generated by the embedded vendor circuit thereat. The test netlist includes at least one pseudo input and the output node, without including a full netlist of either the proprietary or nonproprietary circuits, and can be used to generate scan test vectors for the customer designed integrated circuit by the automatic test vector generating software program.

REFERENCES:
patent: 5903578 (1999-05-01), De et al.
patent: 6223315 (2001-04-01), Whetsel

Affiliated with

Also associated with

Rating

Generating an abbreviated netlist including pseudopin inputs... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Generating an abbreviated netlist including pseudopin inputs..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Generating an abbreviated netlist including pseudopin inputs... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3760191