Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Inventor
active
At-speed ATPG testing and apparatus for SoC designs having...
Generating an abbreviated netlist including pseudopin inputs...
Generating netlist test vectors by stripping references to a...
Mixed-signal core design for concurrent testing of...
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Profile ID: LFUS-PAI-P-2781819