Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-08
2007-05-08
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S711000
Reexamination Certificate
active
10717040
ABSTRACT:
Programmable logic devices (PLDs) including self-repairing RAM circuits, and methods of automatically replacing defective columns in RAM arrays. A RAM circuit including redundant columns is tested during the PLD configuration sequence using a built in self test (BIST) procedure. If a defective column is detected, an error flag is stored in an associated volatile memory circuit. After the BIST procedure is complete, the PLD configuration process continues. The presence of the error flag causes the configuration data to bypass the defective column and to be passed directly into a replacement column. The configuration process continues until the remainder of the circuit is configured, including the redundant column. In other embodiments, the BIST procedure is initiated independently from the PLD configuration process. When a defective column is detected, user operation resumes with data being shunted from the defective column to a redundant column in a fashion transparent to the user.
REFERENCES:
patent: 3995261 (1976-11-01), Goldberg
patent: 4020469 (1977-04-01), Manning
patent: 4700187 (1987-10-01), Furtek
patent: 4899067 (1990-02-01), So et al.
patent: 5153880 (1992-10-01), Owen
patent: 5255227 (1993-10-01), Haeffele
patent: 5459342 (1995-10-01), Nogami et al.
patent: 5485102 (1996-01-01), Cliff et al.
patent: 5498975 (1996-03-01), Cliff et al.
patent: 5513144 (1996-04-01), O'Toole
patent: 5592102 (1997-01-01), Lane et al.
patent: 5742556 (1998-04-01), Tavrow et al.
patent: 5764577 (1998-06-01), Johnston et al.
patent: 5777887 (1998-07-01), Marple et al.
patent: 5889413 (1999-03-01), Bauer
patent: 5914616 (1999-06-01), Young et al.
patent: 6020757 (2000-02-01), Jenkins, IV
patent: 6055205 (2000-04-01), Rao et al.
patent: 6166559 (2000-12-01), McClintock et al.
patent: 6167558 (2000-12-01), Trimberger
patent: 6304101 (2001-10-01), Nishihara
patent: 6344755 (2002-02-01), Reddy et al.
patent: 6356514 (2002-03-01), Wells et al.
patent: 6560740 (2003-05-01), Zuraski, Jr. et al.
patent: 6605960 (2003-08-01), Veenstra et al.
patent: 2002/0120826 (2002-08-01), Venkatraman et al.
patent: 2005/0022065 (2005-01-01), Dixon et al.
U.S. Appl. No. 09/924,365, filed Aug. 7, 2001, Ling et al.
John Emmert et al.; “Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration”; Annual IEEE Symposium on Field-Programmable Custom Computing Machines; Apr. 17, 2000; pp. 165-174.
John M. Emmert et al.; “Incremental Routing in FPGAs”; ASIC Conference 1998. Proceedings, Eleventh Annual IEEE International; Rochester, NY; Sep. 13-16, 1998; pp. 217-221.
Xilinx, Inc.; “Virtex-II Pro Platform FPGA Handbook”; published Oct. 14, 2002; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 19-71.
Lowe Wayson J.
Ngai Tony K.
Wong Jennifer
Cartier Lois D.
Lamarre Guy
Maunu LeRoy D.
Tabone, Jr. John J.
Xilinx , Inc.
LandOfFree
Self-repairing redundancy for memory blocks in programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-repairing redundancy for memory blocks in programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-repairing redundancy for memory blocks in programmable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3738708