Method of and program product for performing gate-level...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000

Reexamination Certificate

active

10435094

ABSTRACT:
A method of fault diagnosis of integrated circuits having failing test vectors with observed fault effects using fault candidate fault-effects obtained by simulation of a set of test vectors, comprises determining a fault candidate diagnostic measure for each fault candidate, the fault candidate diagnostic measure having a fault candidate match metric, an observed fault effect mismatch metric and a fault candidate excitation metric, ranking fault candidates in decreasing diagnostic measure order; and identifying fault candidate(s) having the highest diagnostic measure as the most likely cause of observed fault effects.

REFERENCES:
patent: 5043987 (1991-08-01), Stark et al.
patent: 5127005 (1992-06-01), Oda et al.
patent: 5189365 (1993-02-01), Ikeda et al.
patent: 5515384 (1996-05-01), Horton, III
patent: 5548715 (1996-08-01), Maloney et al.
patent: 5566187 (1996-10-01), Abramovici et al.
patent: 5790565 (1998-08-01), Sakaguchi
patent: 5808919 (1998-09-01), Preist et al.
patent: 5831992 (1998-11-01), Wu
patent: 6134689 (2000-10-01), Mateja et al.
patent: 6185707 (2001-02-01), Smith et al.
patent: 6202181 (2001-03-01), Ferguson et al.
patent: 6308293 (2001-10-01), Shimono
patent: 6324665 (2001-11-01), Fay
patent: 6490702 (2002-12-01), Song et al.
patent: 6516432 (2003-02-01), Motika et al.
patent: 6516433 (2003-02-01), Koenig
patent: 6532440 (2003-03-01), Boppana et al.
patent: 6536007 (2003-03-01), Venkataraman
patent: 6560736 (2003-05-01), Ferguson et al.
patent: 6567946 (2003-05-01), Nozuyama
Song et al., Diagnostic Techniques for the IBM 600 MHz G5 Micriprocessor, 1999 International Test Conference Proceedings, p. 1073-1082.
De et al., “Failure Analysis for Full-Scan Circuits”, 1995 International Test Conference Proceedings, Oct. 21-25, 1995, p. 636-645.
Waicukauski, “Diagnosis of BIST Failures by PPSFP Simulation”, 1987 International Test Conference Proceedings, p. 480-484.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of and program product for performing gate-level... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of and program product for performing gate-level..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of and program product for performing gate-level... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3726542

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.