Method of forming vertical sub-micron CMOS transistors on...

Details Method of forming vertical sub-micron CMOS transistors on... Method of forming vertical sub-micron CMOS transistors on...

2007-05-15

2007-05-15

Graybill, David E. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S198000, C438S199000, C438S268000, C438S276000, C438S279000

Reexamination Certificate

active

10222997

ABSTRACT:
A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

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