Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-12-19
2006-12-19
Fourson, George R. (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S596000, C438S270000
Reexamination Certificate
active
07151024
ABSTRACT:
A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lower thermally dependent leakage currents which enables significantly longer refresh intervals. In certain applications, the cell is effectively non-volatile provided appropriate gate bias is maintained. N-type source and drain regions are provided along with a pillar vertically extending from a substrate, which are both p-type doped. A floating body region is defined in the pillar which serves as the body of an access transistor as well as a body storage capacitor. The cell provides high volumetric efficiency with corresponding high cell density as well as relatively fast read times.
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Fourson George R.
Knobbe Martens Olson & Bear LLP
Parker John M.
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