Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-08-29
2006-08-29
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000
Reexamination Certificate
active
07098130
ABSTRACT:
A method for forming dual damascene features in a dielectric layer. Vias are partially etched in the dielectric layer. A trench pattern mask is formed over the dielectric layer. Trenches are partially etched in the dielectric layer. The trench pattern mask is stripped. The dielectric layer is further etched to complete etch the vias and the trenches in the dielectric layer.
REFERENCES:
patent: 6025259 (2000-02-01), Yu et al.
patent: 6156643 (2000-12-01), Chan et al.
patent: 6514852 (2003-02-01), Usami
patent: 6627540 (2003-09-01), Lee
patent: 6846741 (2005-01-01), Cooney et al.
patent: 2002/0173143 (2002-11-01), Lee et al.
patent: 2003/0119307 (2003-06-01), Bekiaris et al.
Kim Ji Soo
Lee Sang-heon
Reza Sadjadi S. M.
Estrada Michelle
LAM Research Corporation
LandOfFree
Method of forming dual damascene structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming dual damascene structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming dual damascene structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3696224