Method of forming dual damascene structure

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S633000

Reexamination Certificate

active

07098130

ABSTRACT:
A method for forming dual damascene features in a dielectric layer. Vias are partially etched in the dielectric layer. A trench pattern mask is formed over the dielectric layer. Trenches are partially etched in the dielectric layer. The trench pattern mask is stripped. The dielectric layer is further etched to complete etch the vias and the trenches in the dielectric layer.

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patent: 6514852 (2003-02-01), Usami
patent: 6627540 (2003-09-01), Lee
patent: 6846741 (2005-01-01), Cooney et al.
patent: 2002/0173143 (2002-11-01), Lee et al.
patent: 2003/0119307 (2003-06-01), Bekiaris et al.

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