Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-10-03
2006-10-03
Ton, David (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S725000
Reexamination Certificate
active
07117416
ABSTRACT:
A method and apparatus for providing a system-on-a-chip comprising a processor and a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor. The system on a chip further includes a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly.
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Blakely & Sokoloff, Taylor & Zafman
Ton David
Xilinx , Inc.
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