Self-aligned 1 bit local SONOS memory cell and method of...

Details Self-aligned 1 bit local SONOS memory cell and method of... Self-aligned 1 bit local SONOS memory cell and method of...

2006-11-28

2006-11-28

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C438S267000

Reexamination Certificate

active

07141473

ABSTRACT:
A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.

REFERENCES:
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patent: 6413821 (2002-07-01), Ebina et al.
patent: 6559500 (2003-05-01), Torii
patent: 7037781 (2006-05-01), Choi et al.
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patent: 2002/0137296 (2002-09-01), Satoh et al.
patent: 2001-156188 (2001-06-01), None
patent: 2002-0069126 (2002-08-01), None

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