Internal bus testing device and method

Details Internal bus testing device and method Internal bus testing device and method

2006-04-11

2006-04-11

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S043000

Reexamination Certificate

active

07028237

ABSTRACT:
An internal bus testing device for a semiconductor integrated circuit in which an internal bus control circuit and a plurality of modules are linked by a plurality of internal buses. The internal bus testing device includes an area selector which causes the internal bus control circuit to select an address area corresponding to one of the plurality of internal buses. An area address setting unit sets the internal bus control circuit in an internal bus test mode in response to an internal bus test start signal, the area address setting unit storing a state setting signal and a predetermined address value indicating the address area. A control unit supplies, at a start of an internal bus test, the address value from the area address setting unit to the area selector by transmitting the state setting signal from the area address setting unit to the area selector.

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