Method for fabricating a p-type shallow junction using...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S223000, C438S229000, C438S213000

Reexamination Certificate

active

06989302

ABSTRACT:
The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises exposing a portion (125) of an n-type substrate (105) to an arsenic dimer (130). The method also includes forming a p-type lightly doped drain (LDD) region (145) within the portion of the n-type substrate (125). Other embodiments advantageously incorporate the method into methods for making PMOS devices.

REFERENCES:
patent: 6180470 (2001-01-01), Aronowitz et al.
patent: 6265255 (2001-07-01), Hsien
patent: 6372566 (2002-04-01), Kittl et al.
patent: 6429054 (2002-08-01), Krishnan et al.
Chang et al., “Arsenic Dimer Implants for Shallow Extension in .13um Logic Devices”, IEEE, pp. 111-114, 2002.
Peter Kopalidis, Christina Sohl, Brian S. Freer, Michael Ameen, Ros Reece and Mark Rathmell; “Low Energy Implant Throughput Improvement by Using the Arsenic Dimer Ion (As2+) on the Axcelis GSDIII/LED Ion Implanter”; Conference on Ion Implantation Technology; Sep. 22-27, 2002.
Bill Chang, Johathan Chang, A. Agarwal, M.S. Ameen, R. N. Reece, H.I. Chen, Derrick Chien, C.C. Tsai, Mingsheng Tsai. C.L. Weng, D.Y. Wu and C.K. Yang; “Arsenic Dimer Implants for Shallow Extension in 0.13um Logic Devices”; Conference on Ion Implantation Technology, Sep. 22-27, 2002.

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