Method for fabricating semiconductor integrated circuit device

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate

Reexamination Certificate

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C438S765000, C438S770000

Reexamination Certificate

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06962880

ABSTRACT:
A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

REFERENCES:
patent: 3857927 (1974-12-01), Henrie
patent: 4119706 (1978-10-01), Rogers
patent: 4139658 (1979-02-01), Cohen et al.
patent: 4374116 (1983-02-01), Chuang et al.
patent: 4376796 (1983-03-01), Arrasmith et al.
patent: 5360768 (1994-11-01), Ohmi et al.
patent: 5478400 (1995-12-01), Shimizu
patent: 5693578 (1997-12-01), Nakanishi et al.
patent: 5751025 (1998-05-01), Heminger et al.
patent: 5786263 (1998-07-01), Perera
patent: 5840368 (1998-11-01), Ohmi
patent: 5851892 (1998-12-01), Lojek et al.
patent: 5880041 (1999-03-01), Ong
patent: 5959329 (1999-09-01), Tomita et al.
patent: 6037273 (2000-03-01), Gronet et al.
patent: 6110531 (2000-08-01), Paz de Araujo et al.
patent: 6146135 (2000-11-01), Watanabe et al.
patent: 6239041 (2001-05-01), Tanabe et al.
patent: 6362086 (2002-03-01), Weimer et al.
patent: 2001/0006853 (2001-07-01), Tanabe et al.
patent: 2001/0009813 (2001-07-01), Tanabe et al.
patent: 2001/0010975 (2001-08-01), Tanabe et al.
patent: 2001/0024870 (2001-09-01), Tanabe et al.
patent: 2001/0042344 (2001-11-01), Ohmi et al.
patent: 2002/0004315 (2002-01-01), Tanabe et al.
patent: 2002/0019149 (2002-02-01), Tanabe et al.
patent: 0 666 237 (1995-08-01), None
patent: 0 671 761 (1995-09-01), None
patent: 55-003820 (1980-01-01), None
patent: 55-041805 (1980-03-01), None
patent: 57-49895 (1982-03-01), None
patent: 57-82102 (1982-05-01), None
patent: 58-19599 (1983-02-01), None
patent: 59-132136 (1984-07-01), None
patent: 60-107840 (1985-06-01), None
patent: 63-85630 (1988-06-01), None
patent: 5-19746 (1993-03-01), None
patent: 5-114740 (1993-05-01), None
patent: 5-141871 (1993-06-01), None
patent: 5-144804 (1993-06-01), None
patent: 5-152282 (1993-06-01), None
patent: 6-115903 (1994-04-01), None
patent: 6-120206 (1994-04-01), None
patent: 6-163517 (1994-06-01), None
patent: 6-333918 (1994-12-01), None
patent: 7-10935 (1995-02-01), None
patent: 7-86264 (1995-03-01), None
patent: 7-115069 (1995-05-01), None
patent: 7-155069 (1995-05-01), None
patent: 7-19305 (1995-07-01), None
patent: 07-273101 (1995-10-01), None
patent: 07-297181 (1995-11-01), None
patent: 07-297201 (1995-11-01), None
patent: 7-321102 (1995-12-01), None
patent: 8-111449 (1996-04-01), None
patent: 08-213379 (1996-08-01), None
patent: 09-090092 (1997-04-01), None
patent: 09-148315 (1997-06-01), None
patent: 9-148461 (1997-06-01), None
patent: 9-172011 (1997-06-01), None
patent: 10-284484 (1998-10-01), None
patent: 11-067747 (1999-03-01), None
patent: 11-074264 (1999-03-01), None
patent: 11-135492 (1999-05-01), None
patent: 11-162970 (1999-06-01), None
patent: 11-162971 (1999-06-01), None
patent: 11-186248 (1999-07-01), None
patent: 11-186255 (1999-07-01), None
patent: 11-204517 (1999-07-01), None
patent: 11-233508 (1999-08-01), None
patent: WO/9728085 (1997-07-01), None
Nakamura, et al., “Proceedings of the 45thSymposium on Semiconductors and Integrated Circuits Technology”, Dec. 1-2, 1993. (full translation).
Kooi E et al.; “Formation of silicon nitride at a SI-SIO2 Interface during local oxidation of silicon and during heat-treatment of oxidized silicon in NH3 gas” Journal of the Electrochemical Society USA, vol. 123, No. 7, Jul. 1976, pp. 1117-1120.
Supplementary Partial European Search Report for EP 98 90 5758 (completed Feb. 3, 2005).
Tanabe, et al., αDiluted Wet Oxidation: A Novel Technique for Ultra Thin Gate Oxide Formation, In1997 IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings ISSM ′97(Oct. 1997), pp. 49-52.

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