Selective solder bump application

Details Selective solder bump application Selective solder bump application

2005-08-23

2005-08-23

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C438S598000, C438S599000, C438S600000, C438S601000

Reexamination Certificate

active

06933611

ABSTRACT:
Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.

REFERENCES:
patent: 6229219 (2001-05-01), Bhagath et al.
patent: 2001/0052786 (2001-12-01), Eldridge et al.

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