Semiconductor devices having DRAM cells and methods of...

Details Semiconductor devices having DRAM cells and methods of... Semiconductor devices having DRAM cells and methods of...

2005-12-20

2005-12-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S672000, C257S305000

Reexamination Certificate

active

06977197

ABSTRACT:
The present invention discloses a semiconductor device, comprising: bit line landing pads formed over a semiconductor substrate; storage landing pads formed on both sides of the bit line landing pads; a bit line interlayer insulator formed over the whole surface of the semiconductor substrate having the landing pads; a plurality of parallel bit line patterns arranged on the bit line interlayer insulator; bit line insulating layer patterns filling in gate regions between the bit line patterns; upper contact holes formed in the bit line insulating layer patterns to expose side walls of the bit line patterns and located higher than upper surfaces of the bit line patterns; contact hole spacers covering the side walls of the upper contact holes; lower contact holes penetrating the bit line insulating layer patterns and the bit line interlayer insulator below holes surrounded by the contact hole spacers to expose the storage node landing pads and self-alighed with the upper contact holes; and storage node contact plugs filling in the upper and lower contact holes.

REFERENCES:
patent: 6136643 (2000-10-01), Jeng et al.
patent: 2004/0266101 (2004-12-01), Park et al.
patent: 010005108 (2001-01-01), None
patent: 1020020088980 (2002-11-01), None
English language abstract of Korean Publication No. 1020020088980.
English language abstract of Korean Publication No. 010005108.

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