Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-12-06
2005-12-06
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06973636
ABSTRACT:
A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.
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Chang Mi-Chang
Chen Chun-Kuang
Chen Li-Jui
Chou Yu-Jun
Gau Tsai-Sheng
Dinh Paul
Taiwan Semiconductor Manufacturing Company , Ltd.
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