Method and apparatus to facilitate self-testing of a system...

Details Method and apparatus to facilitate self-testing of a system... Method and apparatus to facilitate self-testing of a system...

2005-02-15

2005-02-15

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S732000, C714S736000

Reexamination Certificate

active

06857092

ABSTRACT:
A method and apparatus for providing a system-on-a-chip comprising a processor and a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor. The system on a chip further includes a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly.

REFERENCES:
patent: 5617531 (1997-04-01), Crouch et al.
patent: 6105155 (2000-08-01), Cheng et al.
patent: 6249893 (2001-06-01), Rajsuman et al.
patent: 6408412 (2002-06-01), Rajsuman
patent: 6483344 (2002-11-01), Gupta
patent: 6577158 (2003-06-01), Gupta

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