Method of evaluating core based system-on-a-chip (SoC) and...

Details Method of evaluating core based system-on-a-chip (SoC) and... Method of evaluating core based system-on-a-chip (SoC) and...

2005-09-20

2005-09-20

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C716S030000, C257S672000

Reexamination Certificate

active

06948105

ABSTRACT:
A method of debugging an individual core in core based system-on-a-chip (SOC) ICs with high accuracy and observability, and a structure of SOC incorporating the method. The method includes the steps of building two or more metal layers of a pad frame for each core in an SoC while connecting I/O (input and output) pads on a lower metal layer to a top metal layer, thereby exposing all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, and applying test vector to each core through the I/O pads on the top metal layer of the core and evaluating response outputs of the core received through the I/O pads on the top metal layer.

REFERENCES:
patent: 6218726 (2001-04-01), Chang et al.
patent: 6249893 (2001-06-01), Rajsuman et al.
patent: 6484280 (2002-11-01), Moberly
patent: 2003/0056163 (2003-03-01), Rajsuman et al.

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