High speed vector access method from pattern memory for test...

Details High speed vector access method from pattern memory for test... High speed vector access method from pattern memory for test...

2005-07-05

2005-07-05

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S743000

Reexamination Certificate

active

06915469

ABSTRACT:
A method for applying test vectors to a device under test (DUT) at a speed of the DUT is disclosed. A pattern memory is re-organized into m modules, where m is a DUT/pattern memory speed ratio. Delay circuits in address lines of each module are programmed such that an address signal for a qth module is delayed by (q−1) delay units, where each delay unit is equivalent to one DUT clock cycle. Patterns for each test are stored in these modules according to [n mod m]; where n is a number of patterns in a test. Identical addresses are simultaneously applied to the delay circuits of the m modules according to a fixed address sequence at a rate f equal to or slower than the operating frequency of the pattern memory, such that a period of f is equal to or greater than (m−1) delay units.

REFERENCES:
patent: 5280594 (1994-01-01), Young et al.
patent: 5285421 (1994-02-01), Young et al.
patent: 6014764 (2000-01-01), Graeve et al.
patent: 6243841 (2001-06-01), Mydill

Affiliated with

Also associated with

Rating

High speed vector access method from pattern memory for test... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed vector access method from pattern memory for test..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed vector access method from pattern memory for test... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3427198