Process for integration of a high dielectric constant gate...

Details Process for integration of a high dielectric constant gate... Process for integration of a high dielectric constant gate...

Filed on

2005-07-05

Date issued

2005-07-05

Examiner

Prenty, Mark V. (Department: 2822)

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Field effect device

SubSubClass

Having insulated electrode

Other Related Categories

C257S369000, C257S408000, C257S900000

Type

Reexamination Certificate

Status

active

Patent number

06914313

Description

ABSTRACT:
A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

REFERENCES:
patent: 5491099 (1996-02-01), Hsu
patent: 5880499 (1999-03-01), Oyama
patent: 5970329 (1999-10-01), Cha
patent: 5972762 (1999-10-01), Wu
patent: 6656764 (2003-12-01), Wang et al.
patent: 2004/0087075 (2004-05-01), Wang et al.

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