Method of making a memory cell with polished insulator layer

Details Method of making a memory cell with polished insulator layer Method of making a memory cell with polished insulator layer

Filed on

2005-03-15

Date issued

2005-03-15

Examiner

Chen, Jack (Department: 2813)

Patent Class

Semiconductor device manufacturing: process

SubClass

Making field effect device having pair of active regions...

SubSubClass

Having insulated gate

Other Related Categories

C438S266000

Type

Reexamination Certificate

Status

active

Patent number

06867097

Description

ABSTRACT:
An improved method of making a flash memory cell including a substrate having a floating gate of a first thickness includes depositing an insulator on the substrate and over the floating gate. The insulator is preferably a high quality oxide. A portion of the insulator not covering the floating gate has a second thickness which is greater than the first thickness of the floating gate. The method further includes polishing the insulator until the second thickness is substantially equal to the first thickness. Polishing results in a planar floating gate and insulator layer. The method further includes sequentially depositing a dielectric layer and a control gate layer on the planar floating gate and insulator layer and then etching these layers to complete the stacked gate structure of the memory cell.

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C.Y. Chang and S.M. Sze, “ULSI Technology”, 1996, p. 211.

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