Semiconductor processing methods of forming integrated...

Details Semiconductor processing methods of forming integrated... Semiconductor processing methods of forming integrated...

2005-04-05

2005-04-05

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S194000, C438S197000

Reexamination Certificate

active

06875646

ABSTRACT:
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices. A halo implant is conducted relative to the exposed portions of the source and drain regions. In another embodiment, a common masking step is used and a halo implant is conducted of devices formed over a substrate comprising memory circuitry and peripheral circuitry sufficient to impart to at least three of the devices three different respective threshold voltages.

REFERENCES:
patent: 5272367 (1993-12-01), Dennison et al.
patent: 5371026 (1994-12-01), Hayden et al.
patent: 5534449 (1996-07-01), Dennison et al.
patent: 5661054 (1997-08-01), Kauffman et al.
patent: 5683927 (1997-11-01), Dennison et al.
patent: 5736444 (1998-04-01), Kauffman et al.
patent: 5747855 (1998-05-01), Dennison et al.
patent: 5776806 (1998-07-01), Dennison et al.
patent: 5786249 (1998-07-01), Dennison
patent: 5834851 (1998-11-01), Ikeda et al.
patent: 6004854 (1999-12-01), Dennison et al.
patent: 6008080 (1999-12-01), Chuang et al.
patent: 6054730 (2000-04-01), Noguchi
patent: 6074924 (2000-06-01), Dennison et al.
patent: 6124616 (2000-09-01), Dennison et al.
patent: 6200863 (2001-03-01), Xiang et al.
patent: 6238967 (2001-05-01), Shiho et al.
patent: 6312997 (2001-11-01), Tran
patent: 6337250 (2002-01-01), Furuhata
patent: 6423620 (2002-07-01), Pan et al.
patent: 6455362 (2002-09-01), Tran et al.
patent: 6466489 (2002-10-01), Ieong et al.
patent: 6579751 (2003-06-01), Tran
patent: 6580149 (2003-06-01), Tran et al.
patent: 6620679 (2003-09-01), Tzeng et al.
patent: 20030205745 (2003-11-01), Nam
S. J. Ahn et al., “Novel DRAM Cell Transistor with Asymmetric Source and Drain Junction Profiles Improving Data Retention Characteristics” IEEE, 2002, pp. 176-177.

Affiliated with

Also associated with

Rating

Semiconductor processing methods of forming integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor processing methods of forming integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor processing methods of forming integrated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3374779