Method for forming dual damascene interconnect structure

Details Method for forming dual damascene interconnect structure Method for forming dual damascene interconnect structure

2002-12-18

2004-06-29

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

Reexamination Certificate

active

06756300

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to interconnect technology in integrated circuit fabrication, and more particularly, to a method for forming a dual damascene interconnect structure with enhanced critical dimension of the via opening.
BACKGROUND OF THE INVENTION
Common components of a monolithic IC (integrated circuit) include interconnect structures such as metal lines for electrically connecting integrated circuit devices formed on a semiconductor substrate, as known to one of ordinary skill in the art of integrated circuit fabrication. A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Thus far, aluminum has been prevalently used for metallization within integrated circuits. However, as the width of metal lines are scaled down to smaller submicron and even nanometer dimensions, aluminum metallization shows electromigration failure. Electromigration failure, which may lead to open and extruded metal lines, is now a commonly recognized problem. Moreover, as dimensions of metal lines further decrease, metal line resistance increases substantially, and this increase in line resistance may adversely affect circuit performance.
Given the concerns of electromigration and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
However, copper cannot be easily patterned in a deposition and etch process, and thus, copper interconnect structures are typically formed by forming and filling openings with copper within dielectric material, as known to one of ordinary skill in the art of integrated circuit fabrication.
FIG. 1
for example shows a dual damascene opening
100
formed for fabricating a metal line and a via structure within a dielectric material
101
formed on an underlying interconnect structure
110
that is formed within an underlying dielectric material
103
. The dual damascene opening
100
includes a via opening
102
having a critical dimension
104
and a trench opening
106
having a critical dimension
108
.
The via opening
102
when filled with a conductive fill material forms a via structure, and the trench opening
106
when filled with the conductive fill material forms a metal line. The via structure formed with the via opening
102
couples the metal line formed with the trench opening
106
to the underlying interconnect structure
110
. Such a dual damascene opening
100
is known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIGS. 1 and 2
, the via opening
102
and the trench opening
106
of the dual damascene opening
100
are filled with a conductive fill material
112
such as copper for example. Referring to
FIGS. 2 and 3
, the conductive fill material
112
is polished down until the dielectric material
101
is exposed such that the conductive fill material
112
is contained within the dual damascene opening
100
. The conductive fill material
112
filling the via opening
102
forms the via structure
114
, and the conductive fill material
112
filling the trench opening
106
forms the metal line
116
.
In the case the conductive fill material
112
is comprised of copper, a diffusion barrier material (not shown in
FIGS. 2 and 3
) is also typically formed to surround the copper fill material
112
to prevent the diffusion of copper into the surrounding dielectric material
101
. Copper is a mid-bandgap impurity in silicon, silicon dioxide, and other dielectric materials. Thus, copper may diffuse easily into these common integrated circuit materials to degrade the circuit performance of integrated circuits. To prevent such undesired diffusion of copper, a diffusion barrier layer material is deposited to surround the copper interconnect at the interface between the copper interconnect and the surrounding material, as known to one of ordinary skill in the art of integrated circuit fabrication.
FIGS. 4
,
5
,
6
,
7
, and
8
illustrate cross-sectional views for forming a dual damascene opening according to the prior art. Referring to
FIG. 4
, in the case that the underlying interconnect structure
110
is comprised of copper, a layer of diffusion barrier material
122
is deposited on the underlying interconnect structure
110
and the underlying dielectric material
103
. In addition, a layer of dielectric material
124
for having the dual damascene opening formed therein is deposited on the layer of diffusion barrier material
122
. Then, a layer of via hard-mask material
126
is deposited on the layer of dielectric material
124
, and a layer of trench hard-mask material
128
is deposited on the layer of via hard-mask material
126
.
Referring to
FIG. 5
, a trench mask patterning material
130
(comprised of photo-resist material for example) is deposited and patterned to form a trench opening
132
through the trench mask patterning material
130
and the trench hard-mask material
128
. Referring to
FIGS. 6 and 7
, after formation of the trench opening
132
through the trench hard-mask material
128
, the trench mask patterning material
130
is etched away. Then, referring to
FIG. 7
, a via mask patterning material
133
(comprised of photo-resist material for example) is deposited and patterned to form a via opening
134
through the via hard-mask material
126
.
Referring to
FIGS. 6 and 7
, after forming the via opening
134
through the via hard-mask material
126
, the via mask patterning material
133
is etched away. Then, a portion of the dielectric material
124
exposed through the via opening
134
of the via hard-mask material
126
is etched away such that the via opening
134
extends approximately half-way down the total thickness of the layer of dielectric material
124
in a first etch process.
Referring to
FIGS. 7 and 8
, another etch process is performed for etching away the portion of the via hard-mask material
126
exposed through the trench opening
132
of the trench hard-mask material
128
. In addition, exposed portions of the dielectric material
124
are etched away such that the trench opening
132
extends approximately half-way down the total thickness of the layer of dielectric material
124
. Furthermore, the remaining half of the thickness of the layer of dielectric material
124
and the portion of the diffusion barrier material
122
exposed through the via opening
134
are etched away such that the via opening
134
extends down to the underlying interconnect structure
110
. The trench opening
132
and the via opening
134
form the dual damascene opening
140
.
A disadvantage of the prior art process for forming the dual damascene opening
140
is that a first critical dimension
136
as patterned for the via opening
134
in the via mask patterning material
133
in
FIG. 6
is desired. However, because of mis-alignment during patterning processes, a second critical dimension
138
of the via opening
134
results that is smaller than the desired critical dimension
136
, as illustrated in FIG.
7
. Such smaller critical dimension
138
of the via opening
134
disadvantageously increases the aspect ratio of the via opening
134
which in turn increases the resistance and the probability for electromigration failure of the dual damascene interconnect structure.
Referring to
FIGS. 6 and 7
, the trench hard-mask material
128
may be comprised of a metal such as tantalum, tantalum nitride (TaN), or titanium nitride (TiN), and the via hard-mask material
126
may

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