Methods for fabricating metal silicide structures using an...

Details Methods for fabricating metal silicide structures using an... Methods for fabricating metal silicide structures using an...

2002-09-27

2004-11-09

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S664000, C438S682000

Reexamination Certificate

active

06815275

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to methods for fabricating integrated circuit devices, and more particularly, to methods for fabricating metal silicide structures in integrated circuit devices.
In general, a silicide layer is formed on a gate electrode and junction region of a metal oxide silicon (MOS) transistor to improve the conductive characteristics of the gate electrode and the junction region to reduce RC delay time. Such a silicide layer may be formed of a compound of a silicon material and a refractory metal layer made of cobalt, titanium, or tungsten by a selective deposition method.
A conventional method of fabricating a silicide layer by the selective deposition method will now be described with reference to
FIGS. 1A through 1E
. Referring to
FIG. 1A
, gate insulating layers
14
and gate electrodes
16
are formed on a semiconductor substrate
10
having an isolation layer
12
. Insulating layer spacers
18
are formed at the sidewalls of the gate electrodes
16
by a conventional technique. Next, junction regions
20
are formed in the semiconductor substrate
10
between the gate electrodes
16
. These junction regions
20
function as lightly doped drain (LDD) regions in a MOS transistor. A cobalt (Co) layer
22
is then deposited to a predetermined thickness on the semiconductor substrate
10
.
As shown in
FIG. 1B
, the semiconductor substrate
10
is rapidly thermal-processed (hereinafter, “RTP”) at low temperature, e.g., 450~470° C. The cobalt layer
22
reacts with the gate electrodes
16
and the junction regions
20
below the cobalt layer
22
to form an amorphous cobalt silicide layer (CoxSiy)
24
. Thereafter, a portion of the cobalt layer
22
that does not react with the gate electrodes
16
and the junction regions
20
is removed.
As shown in
FIG. 1C
, a capping layer
26
is formed on the amorphous cobalt silicide layer
24
prior to performing a second RTP on the semiconductor substrate at high temperature. The capping layer
26
prevents the amorphous cobalt silicide layer
24
from being scattered and encroaching adjacent regions of the gate electrodes
16
and the junction regions
20
during the second RTP, when the amorphous cobalt silicide layer
24
is crystallized. Preferably, the capping layer is formed of a material that has stable characteristics at high temperature so as to prevent movement of the amorphous cobalt silicide
24
, and can be used as an etch stopper during a subsequent process of forming contact holes.
Typically, a silicon oxynitride layer (SiON) is used as the capping layer
26
because it has stable characteristics at high temperature and excellent etching selectivity with respect to a silicon oxide interlevel insulating layer. In addition, the silicon oxynitride layer
26
can be formed by plasma-enhanced chemical vapor deposition (PECVD), which is performed at 350-450° C., so as to minimize temperature-related effects on the amorphous cobalt silicide layer
24
positioned below the silicon oxynitride layer
26
. Also, the silicon oxynitride layer
26
can be formed to about 400-600 Å thickness.
Referring to
FIG. 1D
, the second RTP is performed on the semiconductor substrate
10
, including the silicon oxynitride capping layer
26
, at high temperature, e.g., 830-880° C. As a result, the phase of the amorphous cobalt silicide layer
24
is changed into a crystalline cobalt silicide layer (CoSi
2
)
28
having low resistance.
As shown in
FIG. 1E
, an interlevel insulating layer
30
is formed on the capping layer
26
. A predetermined portion of the interlevel insulating layer
30
is etched to expose predetermined portions of the gate electrodes
16
and the junction regions
20
. The exposed capping layer
26
is selectively etched to form contact holes H.
The above conventional method of fabricating integrated circuit devices may have some problems. For instance, the silicon oxynitride capping layer
26
is typically deposited at low temperature in order to minimize temperature-related effects on the amorphous cobalt silicide layer. However, since such a silicon oxynitride layer may have poor step coverage, it may be very difficult to deposit evenly on a semiconductor substrate having a high aspect ratio. This is especially true when the silicon oxynitride layer is formed on a surface having an extreme step, as the silicon oxynitride layer may be rent in the extreme step region.
In the event that the silicon oxynitride layer is not properly deposited, it may not function as an etch stopper when the contact holes H are formed, as shown in FIG.
2
. Also, portions of the junction regions
20
, as well as the cobalt silicide layer
28
, may be hollowed out, which is called ‘pitting’. When the pitting occurs at the junction regions
20
, junction leakage may occur, thus deteriorating the integrated circuit device. Here, “P” denotes a region in which the pitting occurs.
The capping layer
26
can be formed of a silicon oxynitride layer made by low-pressure chemical vapor deposition (LPCVD), which can have excellent step coverage. However, during the LPCVD, the silicon oxynitride layer is typically formed at high temperature, e.g., above 650° C., which would change the characteristics of the amorphous cobalt silicide layer. For this reason, it may be difficult to control the resistance in the cobalt silicide layer.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, a method of fabricating an integrated circuit device comprises forming a refractory metal layer on a silicon-containing substrate, processing the refractory metal layer to form an amorphous metal silicide layer, and depositing an insulating material on the amorphous metal silicide layer. The insulating material is deposited at a temperature that maintains at least a portion of the amorphous metal silicide layer in an amorphous state, to form a capping structure that contains the amorphous metal silicide layer. The method further includes crystallizing the contained amorphous metal silicide layer, and forming an etching stop layer on the capping structure.
In some embodiments of the present invention, the refractory metal layer may comprise cobalt, nickel, titanium, tungsten, and/or tantalum. Depositing of the insulating material may be preceded by removing a portion of the refractory metal layer.
In further embodiments of the present invention, the refractory metal layer may be thermally processed. The amorphous metal silicide layer may be crystallized using thermal processing.
According to some aspects of the invention, the refractory metal layer comprises cobalt. The cobalt-containing refractory metal layer may be thermally processed at 450-470° C. for 25-35 seconds. The amorphous metal silicide layer may be crystallized by thermal processing at 830-880° C. for 40-50 seconds.
In further embodiments of the present invention, depositing of the insulating material comprises plasma-enhanced chemical deposition of the insulating material. Also, the insulating material may comprise at least one of silicon oxynitride, silicon nitride, and silicon dioxide. The insulating material may be deposited to a thickness of about 50 to about 400 Å.
In still further embodiments of the present invention, forming an etching stop layer comprises forming an etching stop layer by low-pressure chemical vapor deposition or by atomic layer deposition. The etching stop layer may comprise at least one of silicon nitride and silicon oxynitride. The etching stop layer may be formed to a thickness of about 150 to about 250 Å.


REFERENCES:
patent: 6071784 (2000-06-01), Mehta et al.
patent: 6284635 (2001-09-01), Jang

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