Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-04-10
2004-08-31
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S700000, C257S753000
Reexamination Certificate
active
06784097
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having a self-aligned contact and a method of manufacturing the same.
2. Description of the Related Art
Increases in the integration of semiconductor memory devices have prompted a reduction in a semiconductor device design rule. In order to meet this trend, contacts are being formed by a self-aligned method.
To form a self-aligned contact, a spacer made of a nitride layer is formed on sidewalls of a conductive pattern such as a gate. Subsequently, an interlayer insulating layer is etched using the nitride layer as an etch stopper. However, if the substrate is exposed during the etching process in this method of forming a spacer and a self-aligned contact, junction damage may result.
FIGS. 1A
to
1
F illustrate cross-sectional views of a conventional process of manufacturing a self-aligned contact of a conventional semiconductor device.
Referring to
FIG. 1A
, a semiconductor substrate
10
made of silicon, for example, includes a self-aligned contact region
11
and a non-self-aligned contact region
12
. A gate insulating layer
13
made of an oxide layer is formed on the semiconductor substrate
10
. A plurality of gates
14
are formed on the gate insulating layer
13
. A mask layer
15
is formed on each of the plurality of gates
14
. Each gate
14
has a single- or a multi-layered structure having a polysilicon layer.
Referring to
FIG. 1B
, the polysilicon layer of the gates
14
undergoes an oxidation process to form an oxide layer
16
. Thereafter, a first nitride layer
17
is formed over the entire surface of the semiconductor substrate
10
.
Referring to
FIG. 1C
, the first nitride layer
17
is anisotropically etched to form a spacer
18
. Here, during the anisotropic etching process, the oxide layer
16
is also etched, whereupon part or all of the gate insulating layer
13
is etched as well.
Referring to
FIG. 1D
, a second nitride layer
19
and an interlayer insulating layer
20
are sequentially formed over the entire surface of the semiconductor substrate
10
.
Referring to
FIG. 1E
, using the second nitride layer
19
as an etch stopper, a portion of the interlayer insulating layer
20
over the self-aligned region
11
is etched. Subsequently, a portion of the second nitride layer
19
and the gate insulating layer
13
over the self-aligned region
11
are etched to form a self-aligned contact
21
as shown in FIG.
1
F.
In the method of forming the conventional self-aligned contact described above, it is possible that during the etching process of the first nitride layer
17
to form the spacer
18
, part or all of the gate insulating layer
13
is also etched, thereby exposing the semiconductor substrate. Therefore, the gate insulating layer
13
cannot satisfactorily serve as a buffer layer for absorbing etching damage when the interlayer insulating layer
20
is etched to form the self-aligned contact
21
. As a result, junction damage may occur.
An ion doping process and a cleaning process are additionally performed subsequent to etching the first nitride layer
17
to form the spacer
18
. During the ion doping process and the cleaning process, the gate insulating layer
13
becomes emaciated, thereby making the junction damage more serious, leading to a significant junction leakage characteristic. Accordingly, a static refresh characteristic of a semiconductor memory device deteriorates.
SUMMARY OF THE INVENTION
In an effort to overcome the problems described above, it is a feature of an embodiment of the present invention to provide a semiconductor device having a self-aligned contact and a method of manufacturing the same, which is capable of preventing junction damage.
It is another feature of an embodiment of the present invention to provide a semiconductor device having a self-aligned contact and a method of manufacturing the same, which is capable of improving a junction leakage characteristic and thus improve a static refresh characteristic in the semiconductor device.
In order to provide these and other features, a preferred embodiment of the present invention provides a semiconductor device having a self-aligned contact, including: a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region; a self-aligned contact exposing a portion of the self-aligned contact region of the semiconductor substrate; a first insulating layer formed on the semiconductor substrate that exposes a portion of the semiconductor substrate corresponding to the self-aligned contact; a plurality of conductive patterns formed on the first insulating layer and spaced apart from each other; spacers formed on sidewalls of each of the plurality of conductive patterns; a second insulating layer formed over the first insulating layer that exposes the self-aligned contact in the self-aligned contact region, and formed over the entire surface of the first insulating layer in the non-self-aligned contact region; a third insulating layer formed between the second insulating layer and the spacer; a fourth insulating layer formed over the entire surface of the non-self-aligned contact region and formed on sidewalls of the spacers over the self-aligned contact region; and a fifth insulating layer formed on a portion of the fourth insulating layer over the non-self-aligned contact region.
The conductive pattern may have either a single- or multi-layered structure preferably made of a polysilicon, and the first insulating layer is preferably a gate oxide layer. The second insulating layer is preferably a high temperature oxide layer formed by an oxidation process for the polysilicon layer. The second insulating layer may serve as a buffer layer to prevent etching damage. The second insulating layer remaining on a portion of the first insulating layer over the non-self-aligned contact region preferably has a thickness of at least about 20 Å. The third insulating layer is preferably formed at a temperature lower than the temperature at which the second insulating layer is formed. Part of the third insulating layer that lies beneath an etched portion of the fourth insulating layer preferably remains on a portion of the second insulating layer over the non-self-aligned contact region. A total thickness of the second and third insulating layers over the non-self-aligned contact region is preferably at least about 20 Å. The fourth insulating layer should have an etching selectivity with respect to the second, the third and the fifth insulating layers. The fourth insulating layer is preferably a nitride layer for an etch stopper. The fifth insulating layer is preferably an oxide layer for an interlayer insulating layer.
An embodiment of the present invention further provides a method of manufacturing a semiconductor device having a self-aligned contact, including: providing a semiconductor substrate having a self-aligned contact region and a non-self-aligned contact region; forming a first insulating layer on the semiconductor substrate; forming a plurality of conductive patterns on the first insulating layer; forming sequentially second, third and fourth insulating layers over the entire surface of the semiconductor substrate; etching the fourth insulating layer to form spacers on sidewalls of the conductive patterns; forming sequentially fifth and sixth insulating layers over the entire surface of the semiconductor substrate; and etching the sixth insulating layer using a portion of the fifth insulating layer over the self-aligned contact region as an etch stopper, and etching the fifth insulating layer to form a self-aligned contact.
The conductive pattern may have a single- or multi-layered structure made of a polysilicon, and the first insulating layer is preferably a gate oxide layer. The second insulating layer is preferably a high temperature oxide layer formed by an oxidation process for the polysilicon layer. The third insulat
Ahn Tae-Hyuk
Kim Myeong-Cheol
Seo Jun
Le Dung A.
Lee & Sterba, P.C.
Samsung Electronics Co,. Ltd.
LandOfFree
Method of manufacturing a semiconductor device with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device with a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3353408