Method for preventing bit line to bit line leakage in memory...

Details Method for preventing bit line to bit line leakage in memory... Method for preventing bit line to bit line leakage in memory...

2001-07-16

2004-08-31

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06784053

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor process, and more particularly, to technologies for fabricating an erasable and programmable read-only memory (EPROM), a flash EPROM and a Flash electrically erasable programmable ROM (Flash EEPROM).
BACKGROUND OF THE INVENTION
FIG. 3
is a schematic top view of a conventional memory cell array. In
FIG. 3
, there are at least word lines
302
and
304
and bit lines
312
and
314
. Theoretically, if the word line
302
and the bit line
312
are turned off, and if the word line
304
and the bit line
314
are turned on, only the cell
320
has an “on” state (other cells have “off” states). However, in fact, some cells theoretically having off states may be judged to have on states, since some current (actually leakage current) has been read through them.
In addition to the reading process, leakage current also brings trouble in the programming process. For example, to make a cell
320
have an on state in a programming process, the cell
320
will be biased until a predetermined voltage is achieved. However, in some cases, the cell
320
already has an on state even though the predetermined voltage has not been achieved, because the cell
320
has leakage current through it. Such leakage current causes the the device to fail. There is therefore a need of a solution for suppressing the leakage current.
SUMMARY OF THE INVENTION
A purpose of the present invention is to improve the characteristic of a memory cell. Another purpose of the present invention is to prevent a memory cell from having bit line to bit line leakage.
To achieve the above or other purposes, the present invention provides a method for suppressing bit line to bit line leakage in a memory cell. In the method, a plurality of word lines are formed on a silicon substrate. A Tetra-ethyl-ortho-silicate (TEOS) oxide layer is then formed on the word lines. Thereafter, the TEOS oxide layer is etched back, to form spacers on the sidewalls of the word lines, whereby the silicon substrate between the word lines is damaged in this etching back step. After the bit lines are annealed, an ion implantation step is performed to implant boron ions into the silicon substrate between word lines by using the word lines and the spacers as masks, for preventing the damage from inducting leakage current.
Implementing the present invention centralizes the implanted ions, and the centralized ions are not thermally diffused to the channel region to decrease the driving force of the devices. Moreover, the narrow width effect is also reduced.
In another aspect, the present invention provides a process for fabricating a memory cell array. A silicon substrate having a plurality of bit lines is provided. A plurality of word lines are formed on the substrate. On the word lines, an oxide layer is deposited. The oxide layer is etched back to form word lines on their sidewalls. An annealing step is performed. After the annealing step is performed, an ion implantation step is performed to implant ions into the silicon substrate between the word lines by using the word lines and the spacers as masks for suppressing the leakage current between the bit lines (bit line to bit line leakage).
In still another aspect, the present invention provides a method for suppressing the bit line to bit line leakage in a silicon substrate. In this method, after the oxide spacers are formed on the sidewalls of word lines of a memory cell array, an ion implantation step is performed to implant ions into the silicon substrate between the word lines by using the word lines and the oxide spacers as masks, for suppressing the bit line to bit line leakage.


REFERENCES:
patent: 5110753 (1992-05-01), Gill et al.
patent: 5479036 (1995-12-01), Hong
patent: 5933732 (1999-08-01), Lin et al.
patent: 6121095 (2000-09-01), Tai et al.
Wolf et al., “silicon Processing for the VLSI Era vol. 1: Process Technology”, Lattice Press, pp. 303-308, 1986.

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