Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2002-11-15
2004-08-03
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S763000, C438S764000, C438S765000, C438S710000
Reexamination Certificate
active
06770570
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices, and more particularly to a method of forming a semiconductor device with a substantially uniform density low-k dielectric layer.
BACKGROUND
Modern advances is semiconductor technology have led to smaller feature sizes and higher density devices. One of the issues that arises as dimensions shrink is the capacitance between adjacent conductors in a device. As individual conductors experience higher parasitic capacitances, the conductors tend to charge more slowly thereby decreasing the peak speeds at which the chip can operate. In addition, it is possible that adjacent conductors can interfere with one another through cross talk.
One technique that has been used to speed up the peak frequency of semiconductor devices is to use conductive materials that have lower resistivity. For example, a copper conductor will have a lower resistance than a similar geometry aluminum conductor. The lower resistance conductor will lower the RC time constant for switching on the lines.
A technique to lower the parasitic capacitance is the use of lower dielectric constant (low-k) materials as the insulator between materials. Silicon dioxide has a dielectric constant of about 4. Materials such as SILK™ available from Dow Chemical or FLARE™ available from Honeywell have a lower dielectric constant that silicon dioxide and have been used in these applications. Other low-k materials include Black Diamond (BD) from Applied Materials and LKD (low k dielectric) from JSR Micro, Inc.
SUMMARY OF THE INVENTION
In several aspects, the present invention relates to a process and device that includes a low-k dielectric insulator. In the preferred embodiment, a low-k dielectric material is deposited This material is then cured using a plasma cure step. The cure process causes the density of the top layer to be increased. The higher density portion, however, also has a higher dielectric constant. As a result, removing this higher density portion can reduce the dielectric constant of the layer. This leads to a lower dielectric constant of the bulk film.
In a first embodiment, a layer of low-k dielectric material is formed. This layer can be a SiCOH layer formed, for example, by chemical vapor deposition or by spin on deposition. A plasma cure is performed on the layer of low-k dielectric material. After performing the plasma cure, a top portion of the layer of low-k dielectric material is removed.
In a more specific embodiment, the present invention has application in a CMOS process, possibly using copper damascene interconnects. In this example, a number of CMOS transistors are formed in a semiconductor region (e.g., substrate, SOI layer, or other). An insulating layer, such as silicon dioxide, is formed over the transistors. A low-k dielectric material can then be formed over the insulating layer and plasma cured. A top portion of the low-k dielectric material is then removed. To form the interconnect, a trench is formed within the low-k dielectric material and filled with a conductive material, e.g., copper.
A preferred embodiment semiconductor device includes a plurality of CMOS transistors. An oxide layer overlies the plurality of transistors and a low-K dielectric layer, such as a SiCOH layer, overlies the oxide layer. The low-k layer has a substantially uniform density of between about 0.5 and about 1.5 and a dielectric constant at or below 3.0. A copper conductor is disposed within a trench in the low-k layer and a plurality of contacts extend through the SiCOH layer and the oxide layer to connect selected ones of the CMOS transistors with the copper conductor.
An advantage of preferred embodiments of the present invention is that the effective dielectric constant of an interlevel dielectric layer can be reduced. The process is relatively simple and does not require any proprietary process steps or any additional masking or other lithography.
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Jang Syun-Ming
Li Lih-Ping
Lu Hsin-Hsien
Berry Renee R.
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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