Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-10
2004-08-10
Guerrero, Maria (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C238S210000, C238S239000, C238S241000, C238S003000
Reexamination Certificate
active
06773982
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to ferroelectric (FE) capacitors and to a method of fabricating the same. More specifically, the present invention relates to an integrated ferroelectric capacitor/CMOS structure which comprises at least a ferroelectric material, a pair of electrodes in contact with opposite surfaces of the ferroelectric material, wherein the electrodes do not decompose at deposition or subsequent processing, and an oxygen source layer in contact with at least one of said electrodes, said oxygen source layer comprising a metal oxide which at least partially decomposes during deposition and/or subsequent processing.
BACKGROUND OF THE PRIOR ART
Recent advances in ferroelectric (FE) materials have led to renewed interest in their use for memory device applications. One of the primary advantages of ferroelectric materials is that they can provide non-volatile memory. Another advantage is that ferroelectric materials have a very high dielectric constant (on the order of 20 or above) associated therewith. The number of applications requiring inexpensive non-volatile memory is rapidly expanding. A breakthrough which would enable cheap integration of non-volatile memory would accelerate this trend.
Ferroelectric materials pose several integration challenges which have not yet been solved. In particular, ferroelectric materials typically require oxygen annealing after deposition of the material in order to operate as a storage medium. This annealing step is preferably carried out after the top electrode of the capacitor and before the BEOL (back end of the line) films are in place. The annealing not only serves to improve the quality of the electrode/ferroelectric interface, but it also repairs damage to the ferroelectric material that may arise from any high energy processing steps, such as an anistropic etching for top electrode and/or ferroelectric patterning. Acceptable device characteristics may further require additional oxygen annealing after BEOL processing, to remove oxygen vacancies created in the ferroelectric material during exposure to hydrogen in steps such as dielectric deposition and forming gas anneals.
The inability of oxygen to permeate the numerous BEOL films limits the effectiveness of anneals towards the end of the wafer fabrication process. In addition, oxygen anneals are typically incompatible with BEOL materials such as Cu, which is easily oxidized, and organic low-k dielectrics, which react with oxygen to form volatiles. These factors present a problem since anneals greatly improve the storage characteristics of the ferroelectric material.
There is thus a great need for developing a method which can be employed in fabricating an integrated ferroelectric/CMOS structure which has improved storage characteristics. Such a method should obviate or mitigate the need for high temperature oxygen anneals at late stages in processing when the BEOL layers are in place. Any method developed should achieve this goal despite difficulties in getting oxygen to permeate through the various BEOL film layers without oxidation damage to any of the BEOL layers.
SUMMARY OF THE INVENTION
One object of the present invention is to provide an integrated ferroelectric/CMOS structure which has improved storage characteristics.
Another object of the present invention is to provide an integrated ferroelectric/CMOS structure wherein sufficient oxygen is present in the integrated structure to obviate or mitigate the need for high temperature oxygen anneals at late stages in processing.
A further object of the present invention is to provide a method of manufacturing an integrated ferroelectric/CMOS structure wherein sufficient oxygen is present therein such that the storage characteristics of the integrated structure is improved upon at least partial release of said oxygen.
A still further object of the present invention is to provide a simple method of fabricating an integrated ferroelectric/CMOS structure which can be used with CMOS technology as well as BEOL technology.
These and other objects and advantages can be obtained in the present invention for both ferroelectric capacitors and non-ferroelectric capacitors containing high-epsilon (&egr;≧20) dielectric materials by utilizing an oxygen source layer in the integrated structure. This oxygen source layer is typically a metal oxide which will at least partially decompose during ferroelectric/high-epsilon material deposition and/or subsequent device processing to release oxygen into the integrated structure, with consequent improvement of device storage characteristics. The decomposition and/or oxygen release temperature, Td, of the oxygen source layer is preferably low enough to allow substantial oxygen release without damage to the layers in the integrated structure (i.e., Td preferably ≦700° C.), yet high enough to insure that complete oxygen release does not occur during BEOL fabrication (i.e., Td preferably ≧350-400° C.). The aforementioned subsequent device processing may additionally include a post-BEOL anneal specifically directed toward releasing the desired amount of oxygen from the oxygen source layer.
In one aspect of the present invention, a ferroelectric capacitor is provided which comprises:
a conductive electrode layer;
a ferroelectric layer disposed on said conductive electrode layer;
a conductive counterelectrode layer formed on said ferroelectric layer; and
an at least partially decomposed oxygen source layer proximate to one of said conductive electrode layers.
The above ferroelectric capacitor may also comprise one or more additional conductive electrode layers. These additional electrode layers can be positioned either above or below the conductive electrode layers of the inventive capacitor. One or more oxygen-impermeable dielectric overlayers can be formed above the uppermost layer of the storage capacitor of the present invention. The conductive electrodes of the ferroelectric capacitor of the present invention may be independently patterned or unpatterned.
The ferroelectric capacitor described above forms part of the integrated ferroelectric/CMOS structure of the present invention. Specifically, the integrated FE/CMOS structure of the present invention comprises:
a CMOS structure having at least one transistor region;
a ferroelectric capacitor formed on said CMOS structure, said ferroelectric capacitor comprising a conductive electrode layer, a ferroelectric layer disposed on said conductive electrode layer, a conductive counterelectrode layer formed on said ferroelectric layer, and an at least partially decomposed oxygen source layer proximate to one of said conductive electrode layers; and
wiring levels formed on said ferroelectric capacitor.
In another aspect of the present invention, a method is provided for fabricating an integrated ferroelectric capacitor/CMOS structure. In accordance with this aspect of the present invention, the method comprises the steps of:
(a) forming at least one complementary metal oxide semiconductor (CMOS) device on a semiconductor wafer;
(b) forming a ferroelectric capacitor over said CMOS device, said ferroelectric capacitor comprising at least one oxygen source layer in proximity to a conductive electrode layer, said oxygen source layer being capable of at least partially decomposing at temperatures below 700° C.;
(c) forming wiring levels on said ferroelectric capacitor at temperatures below 450° C.; and
(d) optionally annealing the structure at a temperature above 300° C. so as to at least partially decompose the oxygen source layer releasing oxygen in the ferroelectric capacitor.
While the above aspects of the invention have been described for ferroelectric capacitors only, it should be understood that the scope of the present invention includes the application of the same inventive aspects and elements to non-ferroelectric capacitors containing high-epsilon dielectric materials.
REFERENCES:
patent: 5466629 (1995-11-01), Mihara et al.
patent: 5624864 (1997-04-01), Arita et al.
patent: 5658820 (1997-08-01), Chung
patent: 5702970
Black Charles Thomas
Cabral, Jr. Cyril
Grill Alfred
Neumayer Deborah Ann
Pricer Wilbur David
Sabo, Esq. William D.
Scully Scott Murphy & Presser
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