Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2002-03-05
2004-02-17
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S791000, C438S795000, C438S908000, C257S297000
Reexamination Certificate
active
06693048
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to annealing processes used to repair process-induced damage in integrated circuits.
2. Description of Related Art
Integrated circuit devices are typically fabricated in mass on silicon wafers. During the fabrication process, a semiconductor wafer is transformed into a multitude of integrated circuits by subjecting it to numerous ordered steps, which may include coating with photoresist resin, exposure of the photoresist to electromagnetic radiation using a reticle affixed to a highly precise stepper device, development of the photoresist to form a mask, oxidation, nitridization, silicidation, wet etching, plasma etching, chemical vapor deposition, plasma-enhanced chemical vapor deposition, sputter deposition, ion implants, and annealing steps for activating and driving implanted ions. A number of these steps create residual damage to the material being treated. For example, plasma etches typically leave dangling silicon bonds. In such a case, the silicon surface exposed to the etch comprises many silicon atoms with unfilled orbitals. Another example is the crystal damage wrought by ion implants. It is axiomatic that the larger the implanted ion, the greater the crystal damage. Arsenic, a relatively large ion, is particularly adept at damaging the silicon crystal structure when implanted. Plasma-enhanced chemical vapor deposition processes can also create damage similar to that caused by plasma etches. In addition, silicon dioxide deposited using plasma-enhanced chemical vapor deposition processes tends to trap electrons. The charge buildup resulting from trapped electrons can shift threshold voltage values in field-effect transistors to the point where they will not fully shut off. Unwanted current leakage through the transistors results.
Following fabrication, but before encapsulation or other packaging steps, the wafers are annealed at temperatures of about 400° C. in a forming gas containing diatomic hydrogen for approximately 30 minutes in order to repair the damage caused by the various process steps. Generally, the forming gas contains both diatomic hydrogen and diatomic nitrogen gases. The partial pressure of hydrogen within the forming gas is usually about 20 percent of the total pressure. At anneal temperatures, nitrogen functions as an inert gas, as it does not react with either hydrogen or the materials from which the circuits were fabricated within this temperature range. Although other inert gases such as helium, neon or argon may be used as components of the forming gas, nitrogen is used primarily for cost considerations. In addition, although forming gases having higher concentrations of hydrogen or even pure hydrogen could be used for the final anneal ambiance, safety concerns dictate that hydrogen be diluted to a partial pressure of around 20 percent of the total pressure. At elevated temperatures, silicon crystals damaged by implanted ions tend to heal themselves. Although the healing process may be less than perfect, a significant reduction in transistor leakage is observed. During the anneal, the hydrogen gas molecules, on account of their small size, are able to diffuse throughout the circuit and react with any dangling bonds that are present. Dangling bonds may be present on silicon atoms in substrate regions which have been plasma etched, in polycrystalline silicon layers which have been plasma etched, and in silicon atoms in silicon dioxide layers which have been formed using plasma-enhanced chemical vapor deposition. The diffusion of hydrogen throughout the oxide layers dissipates trapped charges and enhances circuit performance.
During the fabrication process, an integrated circuit is subjected on numerous occasions to elevated temperature. Generally, the elevated temperature is required to effect a necessary step in the fabrication process. For example, oxidation of silicon, implant activations, and chemical vapor deposition of silicon dioxides are generally performed at temperatures in excess of 500 degrees centigrade. Metallization steps are also performed at high temperatures. Although a certain amount of exposure to elevated temperatures is required both to activate implanted ions and to cause them to diffuse within the implanted material, too much exposure to elevated temperature will effect too great an overlap and counterdoping of adjacent implants having opposite conductivity types and cause source/drain regions of field-effect transistors to diffuse too far into the channel regions. Outdiffusion of dopants into the channel regions is irreversible and will result in transistor leakage. Greater outdiffusion will, at some point, completely destroy the functionality of the circuit. The exposure of integrated circuits to heat is analogous in two respects to the exposure of living organisms to ionizing radiation. Not only is exposure cumulative, but at some exposure level, the organism will die. Each integrated circuit device has an optimum total thermal exposure limit that is generally referred to as the circuit's thermal budget. The budget is calculated by summing all exposures with regard to both time and temperature. Although time is a linear function, the diffusion rate does not increase in direct proportion to the increase in temperature. Instead, the diffusion rate increases geometrically with increasing temperature.
As device geometries are shrunk for new generations of integrated circuits, thermal budgets must be lowered by a corresponding amount. Unless the process is modified to reflect these reduced thermal budgets, it will become increasingly difficult to stay within those budgets. It is a given that final anneals in a hydrogen-containing ambiance for extended periods will become increasingly problematic in terms of thermal budget considerations as device dimensions shrink.
Silicon nitride films are used extensively as moisture barriers in integrated circuits. Silicon nitride films are also nearly impermeable to diatomic hydrogen molecules at standard temperature and pressure. This has not posed a problem until fairly recently, as the silicon nitride film is deposited as the final layer in the fabrication process. The hydrogen anneal step is performed prior to depositing the final silicon nitride film. However, silicon nitride films are also being used with increasing frequency for sidewall spacers and capping layers on field-effect transistor gates when self-aligned contact etches are required for sub-half-micron geometries. These silicon nitride gate structures must be fabricated long before the hydrogen anneal step. The presence of these silicon nitride structures greatly hampers the diffusion of hydrogen molecules into silicon dioxide layers associated with the transistor gates.
Therefore, a new final thermal anneal process is needed that is more compatible with the limited thermal budgets and the silicon nitride gate structures associated with the new generations of integrated circuits.
SUMMARY OF THE INVENTION
This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized, sealed chamber in which a forming gas containing hydrogen is present. Pressurization of the chamber reduces the contribution made by this final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than the prevailing ambient atmospheric pressure. Typical anneal temperatures are within a range of 300 to 500° C. for circuits having aluminum metallization. Higher upper temperature limits and shorter anneal times may be used for circuits employing metallization mate
Lane Richard H.
Wald Phillip G.
Kilday Lisa
Micro)n Technology, Inc.
TraskBritt
LandOfFree
High-pressure anneal process for integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High-pressure anneal process for integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-pressure anneal process for integrated circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3335638