Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-05-20
2004-08-10
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S488000, C438S758000
Reexamination Certificate
active
06773998
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to the use of masks formed of amorphous carbon to form features in integrated circuits.
BACKGROUND OF THE INVENTION
Deep-submicron complementary metal oxide semiconductor (CMOS) is conventionally the primary technology for ultra-large scale integrated (ULSI) circuits. Over the last two decades, reduction in the size of CMOS transistors has been a principal focus of the microelectronics industry.
Transistors (e.g., MOSFETs), are often built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions.
Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million transistors that cooperate to perform various functions for an electronic component. The transistors are generally complementary metal oxide semiconductor field effect transistors (CMOSFETs) which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material. Generally, the gate conductor can be a metal, a polysilicon, or polysilicon/germanium (Si
x
Ge
(1−x)
) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. Conventional processes typically utilize polysilicon based gate conductors because metal gate conductors are difficult to etch, are less compatible with front-end processing, and have relatively low melting points. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
Generally, it is desirable to manufacture smaller transistors to increase the component density on an integrated circuit. It is also desirable to reduce the size of integrated circuit structures, such as vias, conductive lines, capacitors, resistors, isolation structures, contacts, interconnects, etc. For example, manufacturing a transistor having a reduced gate length (a reduced width of the gate conductor) can have significant benefits. Gate conductors with reduced widths can be formed more closely together, thereby increasing the transistor density on the IC. Further, gate conductors with reduced widths allow smaller transistors to be designed, thereby increasing speed and reducing power requirements for the transistors.
As critical dimensions (CDs) of device structures are made smaller, certain issues must be addressed during processing. One such issue involves the use of a wet etch to remove mask layers used in the formation of the structures. When structures having small critical dimensions are produced, the introduction of phosphoric acid or other aqueous etchants to remove a mask layer may damage the structure formed during the etching process.
Another issue that must be addressed is that the shape integrity of the structures formed may be lessened where the materials used to form the mask layer include an internal stress. For example, where a mask material includes an internal compressive or tensile stress by virtue of the microstructure of the material, under certain conditions the mask material may deform. The deformed mask layer will then transfer the deformed pattern into the underlying material when the mask is used during an etch or material removal step. This phenomenon is sometimes referred to as line warpage or “wiggle.” For example, conductive lines formed that exhibit warpage or wiggle characteristics may appear as a serpentine or curving structure. The warpage or wiggle of the line may increase the distance that electrons must travel through the conductive line (and hence increase the resistance of the conductive line) when compared to conductive lines that do not exhibit warpage or wiggle characteristics.
Thus, there is a need to form structures in an integrated circuit using an improved method that produces structures having reduced critical dimensions. Further, there is a need to improve the shape integrity of structures formed during manufacturing (e.g., reducing or eliminating conductive line warpage, etc.). Even further, there is a need to use amorphous carbon as a mask in the formation of integrated circuit structures.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method for producing an integrated circuit. The method includes providing an amorphous carbon layer above a layer of polysilicon material and providing a layer of anti-reflective coating (ARC) material above the amorphous carbon layer. The method also includes removing a portion of the amorphous carbon layer and the layer of ARC material to form an amorphous carbon ARC stack, patterning the layer of polysilicon material according to the amorphous carbon ARC stack, and removing the amorphous carbon ARC stack.
Another exemplary embodiment relates to a method for forming features in an integrated circuit. The method includes depositing a layer of amorphous carbon material above a layer of conductive material and depositing a layer of anti-reflective coating (ARC) material over the layer of amorphous carbon material. The method also includes etching the layer of amorphous carbon material and the layer of ARC material to form a mask. The mask comprises an ARC material portion and an amorphous carbon portion. The method further includes forming a feature in the layer of conductive material by etching the layer of conductive material in accordance with the mask.
A further exemplary embodiment relates to an integrated circuit formed by a method comprising providing a layer of polysilicon above a semiconductor substrate and providing a layer of amorphous carbon above the layer of polysilicon. The method also includes providing a cap layer over the layer of amorphous carbon. The cap layer comprises an anti-reflective coating (ARC) material. The method further includes removing a portion of the cap layer to form a cap feature, removing a portion of the amorphous carbon layer to form an amorphous carbon feature beneath the cap feature, and thinning the cap feature to form a thinned cap layer. The method further includes etching the layer of polysilicon according to the amorphous carbon feature and the thinned cap feature to form a conductive line.
Other principal features and advantages will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
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Bell Scott A.
Bonser Douglas J.
Dakshina-Murthy Srikanteswara
Fisher Philip A.
Lyons Christopher F.
Advanced Micro Devices , Inc.
Foley & Lardner LLP
Fourson George
Toledo Fernando L.
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