Planarization of copper damascene using reverse current...

Details Planarization of copper damascene using reverse current... Planarization of copper damascene using reverse current...

1998-09-25

2004-11-09

Kielin, Erik (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S631000, C438S633000, C438S645000, C438S687000, C438S697000

Reexamination Certificate

active

06815336

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to methods of fabricating copper damascene wiring on a semiconductor wafer, and more particularly to methods of planarizing, without dishing, damascene copper and similar metals.
2. Description of the Related Art
Copper damascene wiring is one of the most promising technologies to reduce the RC delay as well as to perform the shrinkage of interconnect structures. Metal filling not only submicron trenches but submicron holes is the key for damascene wiring. To realize the Cu-damascene wiring, new technologies with excellent step coverage such as metal-organic chemical vapor deposition (MOCVD) and electroplating deposition have been studied. After Cu deposition, the task of the polishing process is to remove only the top of the surfaces and not to encroach on the trench of a patterned sample.
There are several problems which have to be solved before the method of damascening can be widely used.
FIGS. 1
a-c
illustrate typical problems for planarizing damascene using chemical mechanical planarization (CMP) techniques: there is 1) metal remaining on the larger open area(s) and 2) dishing in the wide field regions of the patterns.
Prior art
FIG. 1
a
shows a cross-section of dual damascene trenches
12
,
13
,
14
, and
15
formed in a silicon oxide (SiO
2
)
10
on a silicon semiconductor substrate. A conformal barrier metal layer
16
is deposited on-top of the thus patterned silicon oxide. Layer
16
stops contamination of the SiO
2
by copper
18
, or other metal, which is next deposited over the barrier metal layer, filling the trenches. It can be seen that the surface of the copper damascene is quite uneven as the copper fills the trenches.
FIG. 1
b
shows the silhouette of the copper during CMP. In area
11
(plateau) without trenches the copper is higher than in areas with trenches. The result of further planarization is shown in
FIG. 1
c
. On the plateau there is still copper residue, while the planarization has resulted in dishing of the copper in the trenches. In fact the surface has not been “planarized” as intended.
U.S. Pat. No. 5,602,423 (Jain) shows a damascene process using CMP and electroplating which uses an embedded pillar to prevent damage (e.g. dishing, smearing, overetching). However, this reference differs from the proposed invention.
U.S. Pat. No. 5,567,300 (Datta et al.) describes a high speed electrochemical metal removal technique for planarization of multilayer copper interconnections in thin film modules.
U.S. Pat. No. 5,494,857 (Cooperman et al.) presents a shallow trench isolation planarization method using an etch back process with a reverse tone filler mask and an oxide block in the depressions above the trenches and CMP process.
U.S. Pat. No. 5,346,584 (Nasr et al.) discloses a shallow trench isolation planarization method using an etch back process with a reverse tone filler mask and an oxide filler in the depressions above the trenches and CMP process.
Other patents bear on the forming of copper damascene but do not appear to bear directly on the proposed invention. U.S. Pat. No. 5,693,563 (Teong) shows a method of forming an etch stop for a copper damascene process with CMP.
U.S. Pat. No. 4,954,459 (Avanzino et al.) shows a planarization technique using a reverse mask and etch back only technique.
U.S. Pat. No. 4,789,648 (Chow et al.) shows a method for forming metal interconnects that uses CMP of metal (W or Al alloys).
U.S. Pat. No. 4,702,792 (Chow et al.) discloses a method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias.
C. Y. Chang, S. M. Sze, in
ULSI Technology
, by The McGraw-Hill Company, Inc. copyright 1997, pp. 444-445 discusses damascene and dual damascene techniques.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method to reduce the CMP generated non-uniformity of the wafer surface, the dishing of the copper damascene lines and pads, and the erosion of the silicon oxide layer.
Another object of the present invention is to reduce the time for copper polishing in CMP.
A further object of the present invention is to reduce metal line erosion and to improve metal continuity.
It is yet another object of the present invention to improve the subsequent photo processing by providing a global planar surface.
These objects have been achieved by patterning on the copper damascene a photoresist using a reverse tone photo mask or a reverse tone photo mask of the metal lines, removing excess copper by reverse current plating or dry or wet chemical etching, stripping the photo resist, and planarized by chemical mechanical planarization of the copper damascene. In one embodiment a more relaxed reverse tone photo mask of the metal lines is used, which may be more desirable for practical use.


REFERENCES:
patent: 4702792 (1987-10-01), Chow et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4954459 (1990-09-01), Avanzino et al.
patent: 5256565 (1993-10-01), Bernhardt et al.
patent: 5346584 (1994-09-01), Nasr et al.
patent: 5494857 (1996-02-01), Cooperman et al.
patent: 5567300 (1996-10-01), Datta et al.
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5602423 (1997-02-01), Jain
patent: 5693563 (1997-12-01), Teong
patent: 5969422 (1999-10-01), Ting et al.
patent: 6008116 (1999-12-01), Tran
patent: 6069068 (2000-05-01), Rathore et al.
patent: 6093656 (2000-07-01), Lin
C.Y. Chang et al, “ULSI Technology” The McGraw-Hill Companies, Inc, New York, 1996, p 447.

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