Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2003-04-14
2004-08-17
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S194000, C365S222000
Reexamination Certificate
active
06778459
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuit memory devices and, more specifically, to a method and apparatus for selectively reading antifuse circuits in a memory device.
2. State of the Art
Conventional memory devices, such as synchronous dynamic random access memory (SDRAM), are typically tested to locate defects and failures before being packaged. The memory cells of SDRAM are usually tested to identify defective memory. Predetermined data values are written to selected row and column addresses corresponding to memory cells. Data values are read from the memory cells to determine if the data read matches the data written to those memory cells. If the data read does not match the written data, the memory cells are likely to be defective such that the SDRAM will not operate properly.
To avoid loss of SDRAM memory capacity due to minor defects in memory cells, the SDRAM are fabricated with rows and columns of redundant memory cells which can be substituted for the defective memory cells. Substitution of defective memory cells is accomplished by opening a specific combination of fuses, or closing a specific combination of antifuses, which are located in fuse or antifuse banks on the SDRAM. The combination of fuses or antifuses opened or closed identifies the defective memory cells such that the control components of the SDRAM may identify the defective memory cells and substitute memory cells from the redundant memory cells.
Conventional fuses are resistive devices which may be opened or broken with a laser beam or an electric current. Antifuses are capacitive devices that may be closed or blown by breaking down a dielectric layer in the antifuse with a relatively high voltage. The fuses or antifuses are conventionally arranged in groups such that one group corresponds to a row or column memory address. In this manner, the row or column address of defective memory cells may be identified by closing or opening the fuses or antifuses. For example, if the memory cell addresses in an SDRAM are 8-bit binary addresses, such as an address of 01001001, then the appropriate antifuses in a set of eight (8) antifuses are closed to store the addresses of the defective memory cells. The addresses of the defective memory cells are then determined before the read and write functions of the SDRAM so that redundant memory cells may be used to replace the defective memory cells.
The process of substituting redundant memory cells for defective memory cells in an SDRAM may be better understood with a description of the general layout and processes of an SDRAM.
FIG. 1
illustrates a block diagram of a conventional SDRAM
100
. The SDRAM
100
includes an address register
110
which receives row, column and bank addresses from an address bus
112
. The address bus
112
is generally coupled to a memory controller (not shown). Typically, the row address and bank address received by the address register
110
are applied to a row address multiplexer
116
. The row address multiplexer
116
couples the row address to one of the row address latches
118
depending on the state of the bank address received from the address register
110
. Each of the row address latches
118
stores the row address and applies it to a row decoder (not separately shown) which is part of the address latches
118
. The row decoder applies various signals to a respective memory bank array
120
as a function of the stored row address. The row address multiplexer
116
also couples row addresses to the row address latches
118
for the purpose of refreshing memory cells in the memory bank arrays
120
. The row addresses are generated for refresh purposes by a refresh counter
114
that is controlled by a refresh controller (not shown). The memory bank arrays
120
are comprised of memory cells arranged in rows and columns.
After the row address is applied to the address register
110
and stored in one of the row address latches
118
, a column address is applied to the address register
110
. The address register
110
couples the column address to a column address latch
122
. The column address latch
122
applies a column address to a column decoder
124
which applies various column signals to respective sense amplifiers and associated column circuits
126
for the respective memory bank arrays
120
.
Data to be read from one of the memory bank arrays
120
are coupled from the arrays
120
to a data bus
150
through the column circuit
126
and a read data path that includes a data output register
152
. Data to be written to one of the memory bank arrays
120
are coupled from the data bus
150
through a write data path, including a data input register
154
to the column circuits
126
where they are transferred to one of the memory bank arrays
120
.
The operation of the SDRAM
100
is controlled by a control logic circuit
160
, which includes a command decode circuit
162
and a mode register
164
. The control logic circuit
160
is responsive to high-level command signals received from a control bus
166
through the command decode circuit
162
. The high-level command signals, which are typically generated by the memory controller, are a chip select signal CS#, a write enable signal WE#, a row address strobe signal RAS#, and a column address strobe signal CAS#. The memory controller also typically provides a clock enable signal CKE and a clock signal CLK through the control bus
166
to the control logic circuit
160
. The “#” designates the signal as active low. The control logic circuit
160
generates a sequence of command signals responsive to the high-level command signals to carry out a function (e.g., a read or a write) designated by each of the high-level command signals. The command signals, and the manner in which they accomplish their respective functions, are conventional and well known in the art. Therefore, a further explanation of the command signals will be omitted.
An SDRAM
100
also includes fuse or antifuse banks
170
. When a memory address in the SDRAM
100
is accessed, the memory address is compared to defective memory addresses stored in the antifuse banks
170
to determine whether the incoming address is an address of a defective memory cell. If the memory address corresponds to a defective memory address, a corresponding redundant memory address is accessed instead of the defective memory address sent to the SDRAM
100
. In this manner, rows and columns of defective memory cells may be bypassed and substituted with redundant memory cells.
The antifuse banks
170
generally include banks of antifuses corresponding to column addresses, row addresses, and device options. The column and row antifuses define the addresses of the defective memory cells and the option addresses are used for device configuration and circuit trimming. Each of the column, row and option fuse banks may also be separated into additional banks, for example, a first option fuse bank and a second option fuse bank.
Prior to reading or writing to an SDRAM
100
, the antifuses must be read. In order to guarantee that all of the antifuse banks
170
are properly read, some SDRAMs
100
employ model antifuse circuits to generate a signal of sufficient length to read all of the antifuse banks
170
on the SDRAM
100
. For example, U.S. Pat. No. 5,978,297 describes a model antifuse circuit which accepts a fuse read signal and converts it to a fuse read signal having a duration long enough to assure that all of the antifuse banks on an SDRAM may be read. The disclosure of U.S. Pat. No. 5,978,297 is incorporated herein by reference. When a trigger signal is sent to the model antifuse circuit, an antifuse read signal is created and used to strobe or read all of the antifuses on the SDRAM.
SDRAM specifications often require two auto refresh cycles and a load mode register cycle before an active command is issued. Typically, all of the antifuse banks
170
are strobed or read during each auto refresh cycle and the load mode cycle. R
Dinh Son T.
Micro)n Technology, Inc.
TraskBritt
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