High density plasma CVD process for gapfill into high aspect...

Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering

Reexamination Certificate

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C204S192320, C204S192370, C216S063000, C216S067000, C216S080000, C427S331000, C427S255280, C427S578000, C427S307000, C427S314000, C427S402000, C427S534000

Reexamination Certificate

active

06802944

ABSTRACT:

BACKGROUND OF THE INVENTION
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition (“CVD”). Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. Plasma-enhanced CVD (“PECVD”) techniques, on the other hand, promote excitation and/or dissociation of the reactant gases by the application of radio-frequency (“RF”) energy to a reaction zone near the substrate surface, thereby creating a plasma. The high reactivity of the species in the plasma reduces the energy required for a chemical reaction to take place, and thus lowers the temperature required for such CVD processes as compared to conventional thermal CVD processes. These advantages are further exploited by high-density-plasma (“HDP”) CVD techniques, in which a dense plasma is formed at low vacuum pressures so that the plasma species are even more reactive.
Any of these CVD techniques may used to deposit conductive or insulative films during the fabrication of integrated circuits. For applications such as the deposition of insulation films as premetal or intermetal dielectric layers in an integrated circuit or for shallow trench isolation, one important physical property of the CVD film is its ability to completely fill gaps between adjacent structures without leaving voids within the gap. This property is referred to as the film's gapfill capability. Gaps that may require filling include spaces between adjacent raised structures such as transistor gates, conductive lines, etched trenches or the like.
As semiconductor device geometries have decreased in size over the years, the ratio of the height of such gaps to their width, the so-called “aspect ratio,” has dramatically increased. Gaps having a combination of a high aspect ratio and a small width present a challenge for semiconductor manufacturers to fill completely. In short, the challenge usually is to prevent the deposited film from growing in a manner that closes off the gap before it is filled. Failure to fill the gap completely results in the formation of voids in the deposited layer, which may adversely affect device operation, for example by trapping undesirable impurities.
One process that the semiconductor industry has developed to improve gapfill capability of insulation films uses a multistep deposition and etching process. Such a process is often referred to as a deposition/etch/deposition (“dep/etch/dep”) process. Such dep/etch/dep processes divide the deposition of the gapfill layer into two or more steps separated by a plasma etch step. The plasma etch step etches the upper corners of the first deposited film more than the film portion deposited on the sidewall and lower portion of the gap, thereby widening the gap and enabling the subsequent deposition step to fill the gap without prematurely closing it off. Typically, dep/etch/dep processes can be used to fill higher-aspect-ratio small-width gaps than a standard deposition step for the particular chemistry would allow.
Most of the early dep/etch/dep processes known to the inventors were limited to thermal CVD and PECVD processes. HDP-CVD processes generally have superior gapfill capabilities as compared to these other types of CVD processes because HDP-CVD deposition process provide for a sputtering component to the deposition process simultaneous with film growth. For this reason, HDP-CVD techniques are sometimes referred to as simultaneous dep/etch processes.
It has been found in practice, however, that while HDP-CVD processes generally have better gapfill capabilities than similar non-HDP-CVD processes, for certain gap widths there remains a limit to the aspect ratio of gaps that can be filled. In view of this limit, semiconductor manufacturers have developed various dep/etch/dep techniques for HDP-CVD processes. All of the techniques known to the present inventors employ a single step etch process in which the material deposited in the preceding deposition step is etched using either a physical etch (i.e., anisotropic etch), a chemical etch (i.e., isotropic etch) or an etch step that simultaneously combines physical and chemical components. While a number of these processes are able to produce films having improved gapfill characteristics as compared to other CVD techniques, further improvements and/or alternative approaches are desirable. Such improved processes are particularly desirable in light of the aggressive gapfill challenges presented by integrated circuit designs employing minimum feature sizes of 0.10 microns and less.
BRIEF SUMMARY OF THE INVENTION
Embodiments of the present invention pertain to a high density plasma CVD dep/etch/dep gapfill process that employs a multistep etching technique to widen the entry to the gap being filled after the first deposition step. Embodiments of the invention have superior gapfill capabilities as compared to similar non-dep/etch/dep HDP-CVD processes.
One embodiment of the invention provides a method of depositing a dielectric film to fill a gap or trench formed between two adjacent raised features formed on the substrate. The method includes depositing a first portion of the dielectric film using a high density plasma formed from a first gaseous mixture flown into the process chamber to at least partially fill the gap. The film deposition process is then stopped before or shortly after the entry of the gap pinches off and the film is etched to widen entry to the gap using a multistep etching process that includes a first physical etch step and a subsequent chemical etch step. The physical etch step sputter etches the first portion of film by forming a plasma from a sputtering agent introduced into the processing chamber and biasing the plasma towards the substrate. After the physical etching step, the film is chemically etched by forming a plasma from a reactive etchant gas introduced into the processing chamber. After the etching sequence is complete and entry to the gap has been widened, a second portion of the film is deposited over the first portion by forming a high density plasma from a second gaseous mixture flown into the process chamber to further fill the gap.
According to another embodiment, a method of depositing a silica glass film on a substrate having a trench formed between adjacent raised surfaces of the substrate is disclosed. The method comprises transferring the substrate into a substrate processing chamber and depositing a first portion of the silica glass film over the substrate and within the trench by forming a high density plasma process that has simultaneous deposition and sputtering components from a first deposition gas comprising a silicon source and an oxygen source. Next, deposition of the silica glass film is stopped and a multistep etching process is begun. The first step of the etching process sputter etches the first portion of the film by biasing a high density plasma formed from a sputtering agent introduced into the processing chamber towards the substrate. The next step chemically etches the first portion of the film with reactive species formed from an etchant gas. After the multistep etching sequence, a second portion of the silica glass film is deposited over the substrate and within the trench by forming a high density plasma process that has simultaneous deposition and sputtering components from a second deposition gas comprising a silicon source and an oxygen source.
These and other embodiments of the invention along with many of its advantages and features are described in more detail in conjunction with the text below and attached figures.


REFERENCES:
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patent: 4892753 (1990-01-01), Wang et al.
patent: 4960488 (1990-10-01), Law et al.
patent: 5000113 (1991-03-01), Wang et al.
patent: 5089442 (1992-02-01), Olmer
patent: 5156881 (1992

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