Monos device having buried metal silicide bit line

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S257000, C438S526000, C438S719000, C438S735000

Reexamination Certificate

active

06828199

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor device manufacture, and more particularly, to the fabrication of metal oxide nitride oxide semiconductor (MONOS) cells.
BACKGROUND OF THE INVENTION
FIG. 1
, to which reference is made, illustrates a typical prior art MONOS cell. The cell includes a substrate
10
in which are implanted a source
12
and a drain
14
and on top of which lies an oxide-nitride-oxide (ONO) structure
16
having a layer of nitride
17
sandwiched between two oxide layers
18
and
20
. On top of the ONO structure
16
lies a gate conductor
22
. Between source
12
and drain
14
is a channel
15
formed under ONO structure
16
.
Nitride section
17
provides the retention mechanism for programming the memory cell. Specifically, when programming voltages are provided to source
12
, drain
14
and gate conductor
22
, electrons flow towards
14
. According to the hot electron injection phenomenon, some hot electrons penetrate through the lower section of silicon oxide
18
, and especially if section
18
is thin, they are then collected in nitride section
17
. As is known in the art, nitride section
17
retains a received charge labeled
24
, in a concentrated area adjacent drain
14
. Concentrated charge
24
significantly raises the threshold of the portion of the channel of the memory cell under charge
24
to be higher than the threshold of the remaining portion of the channel
15
.
When concentrated charge
24
is present (i.e., the cell is programmed), the raised threshold of the cell does not permit the cell to be placed into a conductive state during reading of the cell. If concentrated charge
24
is not present, the read voltage on gate conductor
22
can overcome the much lower threshold and accordingly, channel
15
becomes inverted and hence, conductive.
Dopants may be implanted into a substrate to form buried bit lines. Such bit lines are limited in terms of scaling of the semiconductor device, and also are limited in terms of the resistance of the bit line. There is a need for a buried bit line in an MONOS device with very low resistance, thereby allowing scaling down of the bit line and the shrinking of the cell size.
SUMMARY OF THE INVENTION
This and other needs are met by embodiments of the present invention which provide a method of forming an MONOS (metal oxide nitride oxide semiconductor) device, comprising the steps of forming a charge trapping dielectric layer on a substrate, and etching a recess through the charge trapping dielectric layer in accordance with the bit line pattern. A metal silicide bit line is then formed in the recess.
The use of metal silicide in the bit line provides a very low resistance bit line that allows scaling downwardly of the width of the bit line. It reduces the frequency of contacting bit line and allows shrinkage of the cell size. Also, a planar architecture of the bit line may be provided.
In certain embodiments of the invention, a laser thermal annealing process is used to form the metal silicide within the recess in the substrate. The use of laser thermal annealing enables the metal silicide to be formed in a controlled manner, with a low thermal budget and precise application of the laser energy to areas to be silicided.
The earlier stated needs are also met by embodiments of the present invention which provide a metal oxide nitride oxide semiconductor (MONOS), comprising a substrate, a charge trapping dielectric layer on the substrate, and a recess in the charge trapping dielectric layer. A metal silicide bit line is provided in the recess.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


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patent: 0 368 097 (1990-05-01), None

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