Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2002-12-13
2004-02-10
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S751000, C257S789000, C257S793000, C257S774000
Reexamination Certificate
active
06690086
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to the packaging of semiconductor chips, and more particularly to inhibiting damage to semiconductor chip packaging structures during package molding. Now U.S. Pat. No. 6,518,678.
BACKGROUND
The fabrication of packaged semiconductor chips or dies is well known. One conventional ball grid array (BGA) packaging method includes affixing a fabricated die to a substrate and electrically connecting the die to conductive leads on the substrate. The electrical connection may be through wire bonding or other known connection techniques which couples bond pads on the die to corresponding leads on the substrate. A plastic molding material is then typically applied to the die and substrate for encapsulating the die on the substrate. Exposed contacts on the substrate connected to the conductive leads are used to electrically connect the packaged die to a circuit board. The molding material is typically applied by placing the die and substrate in a mold and injecting molding material over the die and substrate and exerting a force by way of a mold clamping mechanism.
A recurrent problem associated with the molding process is that the force applied to the substrate during molding is often greater than the ability of the substrate to resist compression, and thus the force exerted on the die and substrate often damages the delicate wiring and/or the contacts on the substrate, thereby destroying the viability of the packaged product. Further, the compressive forces encountered during molding may cause distortion of the substrate which in turn causes the plastic encapsulation material to leak onto undesired areas of the substrate, producing a defective package for the die.
A conventionally fabricated BGA semiconductor die package
10
is shown in
FIGS. 1-3
. The package
10
includes a die carrier
12
which includes an interposer layer or substrate
14
and a first solder mask layer
16
, which isolates areas of the substrate
14
that are to be bonded to a die
18
supported by the carrier
12
. The substrate
14
has a trench
25
(
FIGS. 2-3
) to allow conductive leads
34
formed on the substrate
14
to interconnect with bond pads
47
on the die
18
. These conductive leads
34
are connected with conductive traces on the substrate
14
, which in turn connect with external contacts
28
. The die
18
is positioned on a surface of the first solder resist layer
16
and has bond pads
47
which connect with respective conductive leads
34
through conductively lined holes
45
provided in the solder mask
16
. The die carrier
12
is diced from a carrier strip, which may include up to twelve separable die carriers. Alternatively, the die carrier may be diced from a carrier matrix, which may include numerous rows and columns of separable die carriers.
Most substrates
14
are formed of either a glass weave reinforced resin or a tape. A second solder mask
20
is provided on a surface
15
of the substrate
14
, leaving exposed the contacts
28
and shielding the conductive leads
34
running along the surface
15
from the contacts
28
to the centrally-located trench
25
. Specifically, located on a surface
15
of the substrate
14
and exposed by openings within the second solder mask layer
20
are the plurality of contacts
28
which will have solder balls screen printed thereon for use in connecting the die package
10
, after package molding, to a printed circuit board. Wiring in the form of the conductive leads
34
is shown extending into the trench
25
to contacts
45
provided in holes in the first solder mask layer
16
to bond pads
47
of the die
18
. Some of the contacts
28
may be formed as openings, such as openings
30
extending through the substrate
14
. After molding, a mold material strip
24
fills the trench
25
on one side of the substrate
14
and provides protection to the wiring
34
extending into the trench
25
to the die
18
. The mold material
24
also covers the die
18
and extends slightly outwardly thereof onto the substrate
14
. The mold material
24
is only partly shown in
FIG. 2
for clarity of illustration.
When a mold material, such as the mold material
24
(FIGS.
1
-
3
), is applied to the die
18
, the substrate
14
, and both solder resist layers
16
,
20
by injection into a mold cavity, a force is exerted on the surface
19
of the die
18
. This causes a compressive force to be exerted down on the substrate
14
squeezing together its opposite surfaces. These compressive forces may destroy the wiring
34
on each surface of the substrate
14
, rendering the packaged product useless. Further, these compressive forces may also cause the mold material strip
24
to weep over the solder mask
20
, creating an undesirable mold material mass
26
(
FIG. 1
) which may cover one or more of the contacts
28
, again rendering the packaged product useless.
SUMMARY
In one aspect, the invention provides a semiconductor die carrier which includes a substrate which has greater resistance to compressive forces. The substrate includes holes extending therethrough which are filled with a material which has a greater resistance to compressive forces than the substrate itself, thereby reducing the possibility of a defective product being produced by compression of the substrate during package molding.
In another aspect, the invention further provides a method of fabricating a semiconductor die package. The method includes forming a substrate having a plurality of holes extending therethrough, filling the plurality of holes with a material which has a greater resistance to compressive forces than the substrate, attaching a die to the substrate, and encapsulating the die and a portion of the substrate with a mold material.
These and other advantages and features of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings.
REFERENCES:
patent: 6030854 (2000-02-01), Mashimoto et al.
patent: 6097089 (2000-08-01), Gaku et al.
patent: 6225694 (2001-05-01), Terui
patent: 6292370 (2001-09-01), Anderson et al.
patent: 6518678 (2003-02-01), James et al.
patent: 10-270600 (1998-10-01), None
James Stephen L.
Rumsey Brad D.
Clark Jasmine
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
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