Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-23
2004-11-16
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000
Reexamination Certificate
active
06818519
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of forming spacers suitable for forming larger S/D (Source/Drain) contact areas and LDD (lightly doped drain)/extension areas and graded junctions for semiconductor devices. More specifically, one embodiment of the invention relates to a method of forming disposable organic spacers using an N
2
plasma etch. Another embodiment of the invention is to use organic spacers as a method of forming semiconductor device features such as larger Source/Drain contact areas with a graded junction or Source/Drain and LDD/extension areas and graded junctions with a single implant step.
BACKGROUND
Formation of organic spacers typically occurs while anisotropic carrying out an etching of polysilicon through openings in a patterned photoresist mask with some formulation which includes one or more of C (carbon), H (hydrogen) and F (fluoride), i.e., C
x
H
y
F
z
. Suitable formulation may include trifluoromethane (CHF
3
) or carbon tetrafluoride (CH
2
F
2
), etc.
U.S. Pat. No. 5,719,089 issued to Meng-Jaw Cherng, et al. on Feb. 17, 1998 discusses the formation of polymer or organic spacers on sidewalls to reduce the size of contact openings in the PMD layer (polysilicon/metal dielectric) using a C
x
H
y
F
z
type plasma etch.
Likewise U.S. Pat. No. 5,861,343 issued to Horng-Haei Tseng on Jan. 19, 1999 also discusses a method of forming a self contact hole on a semiconductor substrate by using a patterned photoresist over a polysilicon layer. The polysilicon is then etched with an RIE process using a reactant gas such as CH
2
F
3
, CF
4
, C
2
F
6
, HB
r
or CH
2
to produce the polymer sidewall spacers. The polymer sidewall spacers are then used as a mask to form an opening in the polysilicon layer of a reduce size.
U.S. Pat. No. 5,866,448 issued to Yelehanka R. Pradeepk et al. on Feb. 2, 1999 describes a method for fabricating an LDD area (lightly doped drain) for self aligned polysilicon gate MOSFET's. According to this patent, a polymer layer is formed along the sidewall of the gate during the patterning process of the gate electrode. This layer is then used to mask the S/D (Source/Drain) ion implantation and, according to the patent, provides improved thickness control as well as an improved sequence of process steps since this requirement for a spacer oxide layer is eliminated.
Another U.S. Pat. No. 6,103,588 issued to Erik S. Jeng on Aug. 15, 2000 also describes a method of forming a contact hole by anisotropic etching of a dielectric oxide layer which forms a spacer on the sidewalls to achieve features smaller than those defined by lithography.
Still other patents that may be considered relevant to the formation of Source/Drain areas and graded junctions include U.S. Pat. Nos. 4,745,086; 5,405,791; 6,103,563; 6,153,455; 6,214,655 and 6,265,253.
SUMMARY OF THE INVENTION
An improved method for forming organic spacers and of using organic spacers for forming larger S/D contact areas, LDD/extension areas and the formation of graded junctions with fewer process steps is provided by the present invention. One embodiment of this invention is a method of forming organic spacers. The method comprises providing a patterned semiconductor structure which is then conformally coated with an organic material such as, for example only, an antireflective coating. The patterned semiconductor structure coated with the organic material is then anisotropically etched with N
2
plasma or “N
2
containing plasma”. “N
2
containing plasma” as used herein is defined as N
2
, which also includes a carrier gas such as, for example, Argon or Helium.
According to another embodiment for forming openings such as a contact via, the step off providing the patterned semiconductor structure is followed by conformally coating the patterned structure with organic material. The anisotropic etching step with N
2
plasma of this coated structure forms organic spacers on the sidewall of the etched aperture in the coated area so that further etching through the patterned semiconductor structure results in a opening with reduced size. This reduced diameter hole or aperture maythen be filled with conductive material.
According to still another embodiment, the invention provides for manufacturing of semiconductor devices with a larger S/D contact area and/or an LDD/extension area, which may include graded junctions with a single implant step. The method of this embodiment of the invention comprises the steps of forming a gate dielectric such as a gate oxide and conductive gate structures. And organic spacers are formed on the sidewall of the conductive gate member. The organic spacers can be formed by the method of this invention or any other known method although the method of this invention is believed to be especially effective. These organic sidewall spacers are then used as a mask to form S/D regions, and LDD/extension areas, which may include enhanced graded junctions. These features may be formed in a single implant step. After forming the S/D region and LDD/extension areas with or without enhanced graded junctions, the organic spacer is stripped and a thinner normal permanent spacer may be formed to provide for larger S/D contact area. Still another embodiment of fanning larger S/D contact areas, which may include graded junctions comprises the steps of forming a gate dielectric such as a gate oxide and conductive gate structures. Thin permanent spacers are then formed over the conductive gate structures. Organic spacers are then formed over the thin permanent spacer by the method of this invention or any other known method. An implanted is performed to form the S/D regions and may include graded junctions. The organic spacers are then stripped to provide larger S/D contact areas.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
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patent: 4994404 (1991-02-01), Sheng et al.
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5670401 (1997-09-01), Tseng
patent: 5719089 (1998-02-01), Cherng et al.
patent: 5801077 (1998-09-01), Chor et al.
patent: 5861343 (1999-01-01), Tseng
patent: 5866448 (1999-02-01), Pradeep et al.
patent: 5989966 (1999-11-01), Huang
patent: 6022782 (2000-02-01), Smith et al.
patent: 6103563 (2000-08-01), Lukanc et al.
patent: 6103588 (2000-08-01), Jeng et al.
patent: 6153455 (2000-11-01), Ling et al.
patent: 6156598 (2000-12-01), Zhou et al.
patent: 6214655 (2001-04-01), Lee et al.
patent: 6265253 (2001-07-01), Lukanc et al.
patent: 6294480 (2001-09-01), Pradeep et al.
patent: 6495430 (2002-12-01), Tsai et al.
patent: 945897 (1999-09-01), None
Clevenger Lawrence
Fang Sunfei
Fourson George
Infineon - Technologies AG
Kebede Brook
Slater & Matsil L.L.P.
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