Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-16
2004-03-02
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S205000, C438S313000, C438S340000, C438S339000, C257S565000, C257S593000, C257SE21371, C257SE29044, C257SE29193, C257S197000
Reexamination Certificate
active
06699741
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to single polysilicon (poly) bipolar transistors and, more particularly, to a single poly bipolar transistor and method that uses a selectively epitaxially grown highly-boron-doped silicon layer as a diffusion source for an extrinsic base region.
2. Description of the Related Art
A bipolar transistor is a three-region device that controllably varies the magnitude of the current that flows through the device. The three regions include a collector, a base that contacts the collector, and an emitter that contacts the base. The charge carriers, which form the current, flow between the collector and the emitter, while variations in the voltage on the base cause the magnitude of the current to vary.
A high frequency bipolar transistor is a transistor that is fast enough to respond to a high frequency input signal. One difference between a standard bipolar transistor and a high frequency bipolar transistor is that the high frequency transistor has a thinner intrinsic base region. As the intrinsic base region gets thinner, the base transit time (the amount of time required for the charge carriers to move through the base) gets smaller, thereby increasing the frequency response of the transistor.
High frequency bipolar transistors are used extensively in RF applications, such as in digital cellular telephones, which operate in the gigahertz frequency range. One problem with high frequency transistors, however, is that the transistors are difficult to fabricate.
FIGS. 1A-1H
show a series of cross-sectional views that illustrate a method of forming a conventional high frequency bipolar transistor.
As shown in
FIG. 1A
, the method utilizes a conventionally-formed wafer
110
that has a substrate layer
112
, such as silicon or oxide, and an n+ buried layer
114
that is formed on substrate layer
112
. In addition, wafer
110
also has a lightly-doped, n-type epitaxial layer
116
that is formed on n+ buried layer
114
.
Wafer
110
further has a deep trench isolation region
120
that isolates epitaxial layer
116
from laterally adjacent regions. A shallow trench isolation region
122
is also formed in epitaxial layer
116
. The shallow trench isolation region
122
separates a collector surface area from a base surface area of epitaxial layer
116
.
In addition, wafer
110
can optionally include an n+ diffused contact region
130
that extends down from the surface of the collector surface area in epitaxial layer
116
to contact n+ buried layer
114
. Contact region
130
is utilized to reduce the series resistance to buried layer
114
. N+ buried layer
114
, n− epitaxial layer
116
, and optional n+ diffused contact region
130
define the collector of the to-be-formed bipolar transistor.
As shown in
FIG. 1A
, the method begins by forming a layer of p-semiconductor material
132
, such as epitaxially grown silicon or silicon germanium, on epitaxial layer
116
, isolation regions
120
and
122
, and region
130
. Following this, a base mask
134
is formed and patterned on layer
132
. The exposed regions of layer
132
are then etched away to form a base region
136
. Mask
134
is then removed.
Next, as shown in
FIG. 1B
, once mask
134
has been removed, a layer of oxide
140
is formed on base region
136
, isolation regions
120
and
122
, and region
130
. After this, a layer of nitride
142
is formed on oxide layer
140
, followed by the formation of an overlying layer of oxide
144
. After this, an intrinsic base mask
146
is formed and patterned on oxide layer
144
.
Next, the exposed regions of oxide layer
144
and underlying layers
142
and
140
are etched away to form an opening
150
that exposes a surface region
152
on the surface of base region
136
. Mask
146
is then removed. One drawback of this method is that, because there is no etch stop, etching to expose surface region
152
can damage or destroy base region
136
.
As shown in
FIG. 1C
, once mask
146
has been removed, a first layer of sacrificial material, such as polysilicon, is formed on oxide layer
144
and surface region
152
to fill up opening
150
. The first layer of sacrificial material is then removed from the surface of oxide layer
144
to form a sacrificial region
154
.
Following this, as shown in
FIG. 1D
, oxide layer
144
is etched until oxide layer
144
has been removed from the surface of nitride layer
142
. After oxide layer
144
has been removed, a second layer of sacrificial material, such as polysilicon, is formed on nitride layer
142
and sacrificial region
154
.
The second layer of sacrificial material is then anisotropically etched to form a sacrificial spacer
156
on nitride layer
142
. After spacer
156
has been formed, wafer
110
is implanted with boron to define a lightly-doped intrinsic base region
158
, and form highly-boron-doped extrinsic base regions
160
on opposite sides of intrinsic base region
158
. The implant damages the lattice and causes defects in regions
160
, the regions that receive the implant.
As shown in
FIG. 1E
, following the implant, sacrificial regions
154
and
156
are removed. Another drawback of this method is that re-etching to expose surface region
152
can again damage or destroy base region
136
/intrinsic base region
158
. Next, as shown in
FIG. 1F
, a layer of polysilicon (poly)
162
is formed on surface region
152
and nitride layer
142
to fill up the opening.
Poly layer
162
can be doped in situ or via ion implantation after formation to have an n+ dopant concentration. Following this, an emitter mask
164
is formed and patterned on poly layer
162
. Next, the exposed regions of poly layer
162
and the underlying layer of nitride
142
are etched away to form an extrinsic emitter
166
. Mask
164
is then removed.
After mask
164
has been removed, wafer
100
is thermally cycled to cause the dopants in extrinsic emitter
166
to out diffuse into base region
136
to form an intrinsic emitter region
170
. The thermal step also anneals the lattice damage caused by the boron implant. Another drawback of this method is that the drive-in/anneal step causes dopants from base region
160
to diffuse into intrinsic base region
158
, thereby widening intrinsic base region
158
. This is because the implantation defects enhance the diffusion of the boron.
After the thermal cycle is complete, a layer of isolation material is formed on emitter
166
and oxide layer
140
. As shown in
FIG. 1G
, the layer of isolation material is then anisotropically etched to form an isolation spacer
172
on oxide layer
140
. As shown in
FIG. 1H
, after spacer
172
has been formed, contacts
174
are conventionally formed through a layer of insulation material
176
.
Thus, the method shown in
FIGS. 1A-1H
suffers from a number of drawbacks, including two etch steps that expose the surface-of the intrinsic base region, and an implant step that causes base-widening dopant diffusion during a subsequent thermal step.
Other prior art methods also suffer from drawbacks. When the intrinsic and extrinsic bases are formed at different points in the process, if the intrinsic base region is formed prior to an extrinsic base polysilicon layer, then the subsequent etch of the extrinsic base polysilicon layer to expose the intrinsic base region can damage or destroy the intrinsic base region because there is no etch stop.
On the other hand, if the extrinsic base polysilicon layer is formed prior to the intrinsic base region, then out diffusion from the heavily-doped extrinsic base region contaminates the lightly-doped intrinsic base region. Thus, there is a need for a method of forming a high frequency bipolar transistor that addresses these drawbacks.
SUMMARY OF THE INVENTION
The present invention provides a high frequency bipolar transistor that has a silicon germanium intrinsic base region that is formed before the extrinsic base regions are formed. A bipolar transistor in accordance with the present inventi
Knorr Christopher John
Sadovnikov Alexei
Everhart Caridad
Keshavan Belur
National Semiconductor Corporation
Pickering Mark C.
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