Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-10-04
2004-12-21
Wilson, Allan R. (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S314000, C257S315000, C438S201000, C438S211000
Reexamination Certificate
active
06833297
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of semiconductor fabrication. More specifically, embodiments of the present invention are directed to a method for reducing drain induced barrier lowering in a memory device.
BACKGROUND ART
Current technology trends are creating increasingly compact semiconductor structures in order to increase circuit density and to improve performance. One technique manufacturers use to scale down the size of semiconductor devices is to decrease the channel length between the source and drain areas. However, as channel length is decreased, device characteristics deviate from those derived from previous long-channel device approximations. These effects are commonly referred to as “short-channel effects.”
FIG. 1
is an exemplary prior art programmable memory device. In device
100
, a channel region
101
is the area of substrate
102
underlying the gate electrode structure
103
. Gate electrode structure
103
comprises a control gate
104
disposed over an Oxide Nitride Oxide (ONO) stack
105
. Control gate
104
is used to control memory device
100
. Beneath ONO stack
105
is floating gate
106
and tunnel oxide layer
107
. ONO stack
105
and tunnel oxide layer
107
insulate floating gate
106
which is the storage element of memory device
100
. Memory device
100
further comprises source
108
and drain
109
.
In a neutral state, there is no conductive path between source
108
and drain
109
. When a positive voltage is applied to control gate
104
and drain
109
, a conductive channel begins to form in channel
101
between source
108
and drain
109
. When the voltage applied to control gate
104
is sufficiently large, the channel between source
108
and drain
109
is completely formed and electrons flow from source
108
and drain
109
. The voltage at which the channel between source
108
and drain
109
forms is called the threshold voltage (V
T
) of device.
Previously, in long-channel devices, conductance in the channel region was effectively controlled by applying a voltage to the gate. However, controlling unintended electrostatic interactions between the source and drain is more difficult to control in short-channel devices. In short-channel devices, as the drain bias is increased, the drain depletion region widens into the channel and can merge with the source depletion region. This results in punch-through leakage between the source and drain and loss of gate control over the device.
This encroachment of the depletion region from the drain into the channel is known as Drain Induced Barrier Lowering (DIBL). DIBL is one of the parameters used to measure the short channel effect in semiconductor devices, and is usually measured as the difference in a device's threshold voltage (V
T
) when different drain biases are applied Strong DIBL is an indication of poor short channel device performance and is especially pronounced in devices with lightly doped substrates.
The increase in leakage current associated with DIBL is especially problematic in flash memory device as they are widely used in very low power applications, for example mobile phones, due to the ability of flash to retain information without applied power. Increases in leakage current may have a significant deleterious effect on total power consumption of the product using the flash device. Furthermore, as DIBL increases, it becomes increasingly difficult to program the memory cell. Therefore, controlling DIBL is becoming increasingly important as the scale of flash memory devices decreases.
The primary and conventional method for controlling DIBL is to increase the doping concentration in the channel area. This has the effect of slowing the encroachment of the drain depletion area into the channel as drain bias increases. However, higher doping concentrations in the channel necessitate using higher threshold voltages (V
T
) to operate the device. This is undesirable because of the need for higher operating voltages and the increased difficulty in erasing the device which slows down erase operations.
Thus, current methods for controlling DIBL in short-channel memory devices are disadvantageous because they necessitate a loss in erase-time performance. Specifically, higher doping concentrations in the channel region necessitate higher operating voltages for the device which make erasing the device more difficult and, therefore, slower. Additionally, because semiconductor processing equipment is extremely expensive, any solution for reducing DIBL should be compatible with existing semiconductor processes and equipment without the need for revamping well established fabrication equipment or processes.
DISCLOSURE OF THE INVENTION
A method for fabricating a memory device which reduces drain induced barrier lowering is disclosed. In one embodiment, a first impurity concentration is deposited in a channel region of a memory device. A second impurity concentration, which overlies the first impurity concentration, is then created in the channel region. Finally, a memory array is fabricated upon the channel region. The memory array overlies the first impurity concentration and the second impurity concentration.
REFERENCES:
patent: 4072868 (1978-02-01), De La Moneda et al.
patent: 4471368 (1984-09-01), Mohsen
patent: 4485390 (1984-11-01), Jones et al.
patent: 4819043 (1989-04-01), Yazawa et al.
patent: 5763921 (1998-06-01), Okumura et al.
patent: 5814854 (1998-09-01), Liu et al.
Fastow Richard M.
He Yue-Song
Wong Nga-Ching
Advanced Micro Devices , Inc.
Wilson Allan R.
LandOfFree
Method for reducing drain induced barrier lowering in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reducing drain induced barrier lowering in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing drain induced barrier lowering in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3274587