Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-12-18
2004-03-16
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C703S015000, C716S030000
Reexamination Certificate
active
06708306
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to electronic design automation, and more particularly to testing and diagnosing failures within an integrated circuit (IC) to determine the cause of the IC failing to perform as expected.
BACKGROUND AND PRIOR ART
The process of determining the root cause of a failing integrated circuit has been vital to the timely and cost effective production of integrated circuits for many years. If the cause of a failure can be determined, the error which causes the failure can often be corrected or prevented from reoccurring. Information about the root cause of the problem can lead to improvements in the design process, the design itself, the manufacturing process, and the test process. It has long been recognized that the capability to determine the root cause of a failure is vital to achieve and maintain high yields in manufacturing, and the manufacturing yields directly affect the cost of manufacturing integrated circuits. The ability to quickly improve yields also allows an IC to become marketable quickly, which directly affects the profitability of the IC.
The entire process describing the prior art methodology for designing and testing ICs including engineering feedback loops is illustrated in FIG.
1
. The process starts with either a high-level design using a high level design language (HDL), followed by synthesis or, alternatively, with a custom design. The results is a schematic (Schm) of the IC. The schematic is used both to create both the physical design (PD), a physical implementation of the schematic, and acting as input to test generation (TestGen) to generate the test patterns to ensure the circuit is performing as designed. The physical design then proceeds to manufacturing, where the IC is built (Build). The IC is then tested (Test) using the test patterns generated by the test generation process. If the test fails, the next step is to determine the root cause of the failure (Diagnose). If the root cause can be determined, information about the root cause can be used to modify the design processes, the test generation processes, or the manufacturing processes in order to prevent the defect from reoccurring.
Many tools have been used historically to determine the cause of test failures. The most important tool to date has been the use of fault simulation to identify a fault whose behavior matches or closely matches the faulty behavior measured at a tester. This process is often referred to as “fault isolation”. The process of fault isolation depends on the capability to model the behavior of a defect as a fault. However, in order to keep the fault simulation process tractable, the kinds of faults typically modeled for fault isolation tend to be simplified models of defect behavior. The most often used example of fault modeling is the “single stuck-at” fault model. In this model, a faulty behavior is modeled as if an internal pin of the integrated circuit is stuck at a single specific logic value (either 0 or 1) for the entire duration of the test. Furthermore, it is assumed that only a single specified internal pin exhibits the faulty behavior, and that the rest of the integrated circuit behaves exactly as it is modeled. The single stuck fault correctly models such defects as a wire that is incorrectly connected to either a voltage source, or to ground. For simple integrated circuit (IC) technologies, the single stuck fault model along with the process of fault isolation has proven practical to determine to cause of integrated circuit failures for many years. However, as technology becomes more complex, as the density of the wiring gets higher, as the speeds at which the circuits are expected to behave gets faster and faster, and as the voltage used to drive the circuits get lower and lower, many new secondary failure mechanisms are now more important to understand and prevent. In these cases, the process of fault isolation using a simple single stuck at fault model is not sufficient to identify the root cause of most of these more complicated failure mechanisms. More details regarding fault simulation and fault isolation may be found in several references, such as a textbook by P. K. Lala “Fault Tolerant & Fault testable Hardware Design” published by Prentice Hall Intl., Inc. 1985.
The intent of the present invention is to provide more information about the environment that exists in the IC when it fails. An IC can be modeled as a combination of logic gates and memory elements that are connected by electrical nets. The logic gates consist of one or more inputs connected to nets, and at least one output whose value depends of the value of the inputs. For instance, a two input AND gate has an output value of 1 only when both inputs are 1, and a value of 0 otherwise. A memory or sequential element is a gate which also has inputs and an output, although the memory element can capture a value and retain that value over time. For instance, a level sensitive latch captures the value on a data input pin when the clock input is at 1, and retains that value when the clock input is at 0. A test of the circuit consists of stimulating the inputs of the circuit and forcing values to propagate through the gates and memory elements to the point where the results of the simulation can be measured at the output pins of the circuit. At a tester, the measured results are compared against expected results. If the measured results are different than the failing results, the circuit fails the test. In the course of a single test, each net may take on many different logic values. The logic values on all internal nets at any given time can be considered a “circuit state”. Thus, an IC may go through several circuit states within a single test. The single stuck fault model simulates a defect which affects a single net in every circuit state. However, failures which do not behave like a single stuck fault often do not exhibit such static behavior. Instead, these defects only manifest themselves when specific conditions occur in the circuit state.
One example of a failure mechanism which does not behave like a stuck fault is a “shorted net” fault. Often, when wires in the IC are close together, a piece of foreign material may connect two wires together. When such a short occurs, there are several ways in which incorrect results may occur. For this example, assume that one of the two shorted nets is electrically ‘stronger’ than the other. In this case, the value on the weak net will be overridden by the value on the strong net. The result is that the weaker net will behave like a single stuck-at-0 fault when the stronger net is at 0, but the weaker net will behave like a stuck-at-1 fault when the stronger net is at 1. Furthermore, the failure cannot produce an incorrect measure value unless the strong net is at a value that is different from the value at which the weaker net is supposed to be. Such a failure mechanism cannot be modeled with a single stuck fault model. In this case, the circuit will fail only when the strong net is opposite from the weak net.
OBJECTS OF THE INVENTION
Accordingly, it is a primary object of the invention to diagnose failures occurring within an integrated circuit (IC) by determining the root cause of the IC failing to perform as expected.
It is a further object to determine the necessary conditions in the circuit state under which a failure occurs.
It is another object to determine that every time a failure in the form of a short occurs, the strong net is at a value opposite to the value expected in the weak net.
It is yet another object to determine that every time the circuit does not fail, the weak net and the strong net are expected to be at the same value.
It is still another object to identify a dominant net within the logic given a candidate dominated net (available from analysis of traditional stuck fault diagnostics.
It is a more particular object to identify within the logic the other net that participates in the short given one net of a shorted net pair that behaves like an AND or OR.
It is yet another
Bartenstein Thomas W.
Swenton Joseph M.
Cadence Design Systems Inc.
Lamarre Guy J.
Orrick Herrington & Sutcliffe LLP
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