Joseph M. Swenton

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Analysis of untestable faults using discrete node sets

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Method for diagnosing failures using invariant analysis

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method to improve a testability analysis of a hierarchical...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Profile ID: LFUS-PAI-P-1963191

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