Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-26
2004-04-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S424000, C438S427000, C438S445000, C438S430000
Reexamination Certificate
active
06727150
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of forming trench isolation within semiconductor substrates.
BACKGROUND OF THE INVENTION
In modern semiconductor device applications, numerous devices are packed onto a single small area of a semiconductor substrate to create an integrated circuit. Many of the individual devices are electrically isolated from one another. Accordingly, electrical isolation is an integral part of semiconductor device design for preventing unwanted electrical coupling between adjacent components and devices.
As the size of integrated circuits is reduced, the devices that make up the circuits are positioned closer together in order to comply with the limited space available on a typical semiconductor substrate. Conventional methods of isolating circuit components use trench isolation regions. Such are formed by etching trenches into a semiconductor substrate and filling the trenches with insulative material. Trench isolation regions are commonly divided into three categories: shallow trenches (STI) (trenches less than about 1 micron deep); moderate depth trenches (trenches of from about 1 to about 3 microns deep); and deep trenches (trenches greater than about 3 microns deep). As the density of components on the semiconductor substrate increased, the widths of the trenches have also decreased.
Trench isolation regions, particularly STI regions, can develop voids in the dielectric material during the process to fill the trenches. As the dielectric material flows to an edge between a substrate surface and a sidewall of the trench, constrictions develop at the top of trenches due to the narrow opening in the trench. As the dielectric material flows into the trench, the constrictions can develop into voids moving into the trench with the dielectric material.
While the invention was motivated in addressing the above issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded (without interpretative or other limiting reference to the above background art description, remaining portions of the specification or the drawings) and in accordance with the doctrine of equivalents.
SUMMARY
The invention includes methods of forming trench isolation within semiconductor substrates. In one implementation, a method of forming trench isolation within a semiconductor substrate includes forming a first isolation trench of a first open dimension within a semiconductor substrate. The first isolation trench has a base. A second isolation trench is formed into the semiconductor substrate through the base of the first isolation trench. The second isolation trench has a second open dimension along a line parallel with the first open dimension which is less than the first open dimension. Insulative isolation material is formed within the first and second isolation trenches. The insulative isolation material has a void therein extending from within the second isolation trench to the first isolation trench.
In one implementation, a method of forming trench isolation within a semiconductor substrate includes forming a sacrificial masking layer over a semiconductor substrate. A first isolation trench of a first open dimension is etched through the sacrificial masking layer and into the semiconductor substrate. The first isolation trench has sidewalls between which the open dimension spans. The first isolation trench has a base. Anisotropically etched insulative sidewall spacers are formed over the first isolation trench sidewalls. The spacers have elevationally outermost surfaces which are received elevationally lower than an elevationally outermost surface of the sacrificial masking layer. A second isolation trench is etched into the semiconductor substrate through the base of the first isolation-trench between and substantially selectively to the sidewall spacers. The second isolation trench has a second open dimension along a line parallel with the first open dimension and is less than the first open dimension. Insulative isolation material is formed within the first and second isolation trenches.
Other aspects and implementations are contemplated.
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Holt et al.,A Novel T-Shaped Shallow Trench Isolation Technology, 40 JPN. J. Appl. Phys. Part 1, No. 4B, pp. 2616-2620 (Apr. 2001).
U.S. patent application Ser. No. 09/960,119, Trivedi, filed Sep. 21, 2001.
Micro)n Technology, Inc.
Niebling John F.
Pompey Ron
Wells St. John P.S.
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