Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-01-24
2003-12-09
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S128000, C438S269000, C438S398000
Reexamination Certificate
active
06660584
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of memory cell arrays and, more particularly, to the formation of a specialized bit line contact in the structure of a DRAM array.
Conventional memory device arrays include word lines running generally in parallel along one direction and bit line pairs running generally in parallel along a perpendicular direction. The memory cell includes a charge storage structure connected by a transistor to one of the bit line pairs. Each transistor is activated by a word line. A row of memory cells is selected upon activation of a word line. The state of each memory cell in the row is transferred to a bit line for sensing by sense amplifiers, each of which is connected to a pair of bit lines. The memory cell transfer transistors are formed in the substrate in a plurality of continuous active areas running generally in parallel to each other. To form a transistor in an active area, impurity doped regions are formed in the substrate along the length of each active area
24
to create the source and drain of the transistor. A word line forms the gate of the transistor. The transistor formed in the active area provides the pass gate that is controllable to electrically connect the charge storage structure to a bit line. Thus, for example, activation of a word line will cause stored charges to be transferred by corresponding transistors to bit lines. The bit lines are electrically connected to a node of the transistor by bit line contacts.
Conventional bit line contacts are formed through a multi-step deposition and etch back process that increases the complexity of the overall array fabrication process. The process is further complicated because the upper surface of the bit line contact, i.e., the surface that serves as the conductive interface with the bit line, defines a V-shaped profile. Accordingly, there is a need for a memory array fabrication scheme that presents a simplified bit line contact fabrication process.
BRIEF SUMMARY OF THE INVENTION
This need is met by the present invention wherein an improved bit line contact fabrication process is provided. In accordance with one embodiment of the present invention, a memory cell defined along first, second, and third orthogonal dimensions is provided. The first dimension is characterized by one-half of a bit line contact feature, one word line feature, one word line space feature, and one-half of a field poly line feature. The second dimension is characterized by two one-half field oxide features and one active area feature. The first and second dimensions define a 6F
2
memory cell. The bit line contact feature is characterized by a contact hole bounded by insulating side walls. The contact hole is filled with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile. The storage node contact feature may also comprise a conductively doped polysilicon plug defining a substantially convex upper plug surface profile.
The insulating side walls may comprise a first pair of opposing insulating side walls along the first dimension and a second pair of opposing insulating side walls along the second dimension. The first pair of opposing insulating side walls may comprise respective layers of insulating spacer material formed over a conductive line. The second pair of opposing insulating side walls may comprise respective layers of insulating material formed between respective contact holes. The contact hole may be filled with the polysilicon plug to an uppermost extent of the insulating side walls.
In accordance with another embodiment of the present invention, a memory cell array is provided including a plurality of memory cells, each of the memory cells being defined along first, second, and third orthogonal dimensions. The first dimension is characterized by one-half of a bit line contact feature, one word line feature, one word line space feature, and one-half field poly line feature. The second dimension is characterized by two one-half field oxide features and one active area feature. The first and second dimensions define a 6F
2
memory cell. The bit line contact feature is characterized by a contact hole bounded by insulating side walls. The contact hole is filled with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile.
In accordance with yet another embodiment of the present invention, a computer system is provided comprising a microprocessor in communication with a memory device including a memory cell array, the memory cell array including a plurality of memory cells, each of the memory cells being defined along first, second, and third orthogonal dimensions. The first dimension is characterized by one-half of a bit line contact feature, one word line feature, one word line space feature, and one-half field poly line feature. The second dimension is characterized by two one-half field oxide features and one active area feature. The first and second dimensions define a 6F
2
memory cell. The bit line contact feature is characterized by a contact hole bounded by insulating side walls. The contact hole is filled with a conductively doped polysilicon plug defining a substantially convex upper plug surface profile.
In accordance with yet another embodiment of the present invention, a memory cell is provided comprising an electrically conductive word line, an electrically conductive bit line, an electrical charge storage structure, a transistor structure, and a bit line contact. The charge storage structure is conductively coupled to the bit line via the transistor structure and the bit line contact. The transistor structure is conductively coupled to the word line. The bit line contact comprises a conductively doped polysilicon plug formed within a contact hole bounded by insulating side walls. The doped polysilicon plug defines a substantially convex upper plug surface profile in contact with the bit line.
In accordance with yet another embodiment of the present invention, a memory cell array is provided comprising electrically conductive word lines and bit lines, an array of electrical charge storage structures, an array of transistor structures, an array of bit line contacts, and a plurality of sense amplifiers. Each of the charge storage structures is conductively coupled to one of the bit lines via a selected transistor structure and a selected bit line contact. Each of the transistor structures is conductively coupled to one of the word lines. Each of the bit lines are conductively coupled to one of the sense amplifiers. Each of the selected bit line contacts comprises a conductively doped polysilicon plug formed within a contact hole bounded by insulating side walls. Each of the doped polysilicon plugs define a substantially convex upper plug surface profile.
In accordance with yet another embodiment of the present invention, a computer system is provided comprising a microprocessor in communication with a memory device including a memory cell array, the memory cell array including electrically conductive word lines and bit lines, an array of electrical charge storage structures, an array of transistor structures, an array of bit line contacts, and a plurality of sense amplifiers. Each of the charge storage structures is conductively coupled to one of the bit lines via a selected transistor structure and a selected bit line contact. Each of the transistor structures is conductively coupled to one of the word lines. Each of the bit lines are conductively coupled to one of the sense amplifiers. Each of the selected bit line contacts comprises a conductively doped polysilicon plug formed within a contact hole bounded by insulating side walls. Each of the doped polysilicon plugs define a substantially convex upper plug surface profile.
In accordance with yet another embodiment of the present invention a memory cell is provided. The memory cell is defined along first, second, and third orthogonal dimensions and comprises an electrically conductive word line, an electrically cond
Huynh Yennhu B.
Jr. Carl Whitehead
LandOfFree
Selective polysilicon stud growth of 6F2 memory cell... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Selective polysilicon stud growth of 6F2 memory cell..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective polysilicon stud growth of 6F2 memory cell... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3184431