Method of making high density semiconductor memory

Details Method of making high density semiconductor memory Method of making high density semiconductor memory

2002-07-09

2003-11-18

Thompson, Craig (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06649467

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor memories and, more particularly, to an improved dynamic random access memory (DRAM) and method for making such a DRAM wherein a plurality of memory cells are aligned with one another along a pair of wordlines with each wordline being connected to access alternate ones of the memory cells to provide a DRAM having a reduced memory cell size in relation to the superior signal-to-noise performance of the memory.
While device density in DRAM's is of course limited by the resolution capability of available photolithographic equipment, it is also limited by the form of the individual memory cells used to make the DRAM's and the corresponding areas of the memory cells. The minimum area of a memory cell may be defined with reference to a feature dimension (F) which ideally refers to the minimum realizable process dimension; however, in reality F refers to the dimension that is half the wordline WL pitch (width plus space) or digitline DL pitch (width plus space). Wordline pitch WP and digitline pitch DP are shown in
FIG. 1
which illustrates aligned memory cells used to form a DRAM wherein all memory cells along a wordline are simultaneously accessed and the area of each memory cell is 3F·2F=6F
2
.
Reference is made to
FIG. 1
to illustrate this definition of cell area wherein the 6F
2
memory cell
100
is for an open digitline array architecture. In
FIG. 1
, a box is drawn around the memory cell
100
or memory bit to show the cell's outer boundary. Along the horizontal axis of the memory cell
100
, the box includes one-half digitline contact feature
102
, one wordline feature
104
, one capacitor feature
106
and one-half field oxide feature
108
, totaling three features. Along the vertical axis of the memory cell
100
, the box contains two one-half field oxide features
112
,
114
and one active area feature
116
, totaling two features such that the structure of the memory cell
100
results in its area being 3F·2F=6F
2
.
FIG. 2
illustrates another memory cell which is used to produce DRAM's having superior signal-to-noise performance and wherein the area of each memory cell
120
is 4F·2F=8F
2
. The 8F
2
memory cell
120
of
FIG. 2
is for a folded array architecture and a box is drawn around the memory cell
120
or memory bit to show the cell's outer boundary.
Along the horizontal axis of the memory cell
120
, the box includes one-half digitline contact feature
122
, one wordline feature
124
, one capacitor feature
126
, one field poly feature
128
and one-half field oxide feature
130
, totaling four features. Along the vertical axis of the memory cell
120
, the box contains two one-half field oxide features
132
,
134
and one active area feature
136
, totaling two features such that the structure of the memory cell
120
results in its area being 4F·2F=8F
2
.
The increased memory cell area is due to the staggering of the memory cells so that they are no longer aligned with one another which permits each wordline to connect with an access transistor on every other digitline. For such alternating connections of a wordline, the wordline must pass around access transistors on the remaining digitlines as field poly. Thus, the staggering of the memory cells results in field poly in each memory cell which adds two square features to what would otherwise be a 6F
2
structure.
Although the 8F
2
staggered memory cells are 25% larger than the aligned 6F
2
memory cells, they produce superior signal-to-noise performance, especially when combined with some form of digitline twisting. Accordingly, 8F
2
memory cells are the present architecture of choice.
There is an ongoing need to produce high performance DRAM's which include more memory cells within the same area of DRAM real estate. In particular, it would be desirable to be able to produce DRAM's having aligned 6F
2
memory cells which have substantially the same superior signal-to-noise performance found in DRAM's having staggered 8F
2
memory cells.
SUMMARY OF THE INVENTION
This need is currently being met by the methods and apparatus of the present invention wherein an improved dynamic random access memory (DRAM) includes a plurality of memory cells aligned with one another along a pair of wordlines with each wordline being connected to access alternate ones of the memory cells to provide a DRAM having reduced memory cell area and superior signal-to-noise performance. In particular, as illustrated, the improved DRAM has aligned memory cells having cell areas of 6F
2
yet exhibiting substantially the same superior signal-to-noise performance found in DRAM's having staggered 8F
2
memory cells.
The improved DRAM memory cells are formed by transistor stacks which are aligned along and interconnected by wordlines extending between and included within the transistor stacks. By forming the wordlines as a part of the transistor stacks, the wordlines are narrow ribbons of conductive material. During formation of the transistor stacks, the wordlines are connected so that a first wordline controls access transistors of every other one of the memory cells and a second wordline controls the access transistors of the remaining memory cells. Thus, the first wordline accesses a first series of alternate memory cells, such as the odd memory cells, and the second wordline accesses a second series of alternate memory cells, such as the even memory cells, with the first and second series of memory cells being interleaved with one another.
As illustrated, two memory cells are incorporated into a memory cell pair with the two memory cells sharing a digitline. For such memory cell pair structures, first and second wordlines are formed into transistor stacks forming first access transistors of the memory cell pairs and third and fourth wordlines are formed into transistor stacks forming second access transistors of the memory cell pair. The two transistor stacks are separated from one another by a digitline which is connected to first and second capacitors formed on the other sides of the transistor stacks by the access transistors to form the DRAM.
It is an object of the present invention to provide an improved DRAM having superior signal-to-noise ratio for the area of the memory cells making up the DRAM; to provide an improved DRAM wherein aligned memory cells are formed along a pair of wordlines with one of the wordlines being connected to access alternate ones of the memory cells and the other wordline being connected to access the remaining memory cells; and, to provide an improved DRAM wherein memory cells include transistor stacks and are aligned along and interconnected by wordlines extending between and included within the transistor stacks.
Other objects and advantages of the invention will be apparent from the following description, the accompanying drawings and the appended claims.


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