Nitride read only memory cell

Details Nitride read only memory cell Nitride read only memory cell

2001-11-14

2003-02-04

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S216000, C438S238000, C438S258000

Reexamination Certificate

active

06514831

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a nitride read only memory (NROM) device.
2. Description of Related Art
Due to the rapid developments of the semiconductor techniques and widespread application of information products, semiconductor devices now play an important role, specifically, in the flash memory. This memory has excellent program/erase characteristics and has been a master trend in the nonvolatile memory field. However, considering transistor integrity, power consumption, threshold voltage level and noise reduction, the flash memory cannot be exactly programmed or erased in the period of data access.
A typical structure of a NROM cell includes a stack composed of a bottom oxide layer, a nitride layer, a top oxide layer and conductive layer on a substrate. Two source/drains in the substrate are located on two sides of the stack to serve as bit lines. In the NROM cell, the nitride layer serves as a floating gate in the traditional flash memory to store charges, and the conductive layer serves as a control gate, which is used as a word line, on the traditional flash memory.
In U.S. Pat. No. 5,966,603, the surfaces of the source/drains are thermally oxidized to form bit line oxides, and the exposed surface of the nitride layer are thermally oxidized, too. Therefore, the charge retention time can be increased and the bit line capacitance can be decreased. But during the thermal oxidation period, the source/drains suffer seriously lateral diffusion, which limits the extent of device reduction.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a NROM cell to increase the charge retention time.
It is another an objective of the present invention to provide a method of fabricating a NROM cell to decrease the thermal budget.
It is still another an objective of the present invention to provide a method of fabricating a NROM cell to limit the lateral diffusion of source/drains.
In accordance with the foregoing and other objectives, the present invention provides a nitride read only memory (NROM) cell. The NROM cell comprises a composite gate dielectric on a substrate, a conformal oxide layer on the surface of the composite gate dielectric, two bit line oxides in the substrate located on two sides of the composite gate dielectric, two source/drains respectively located under the two bit line oxides, and a gate over the composite gate dielectric and the two bit line oxides. The composite gate dielectric comprises a bottom oxide layer, a nitride layer and a top oxide layer, and the conformal oxide layer is deposited by chemical vapor deposition.
This invention also provides a method of fabricating a NROM cell. A bottom oxide layer, a nitride layer and a top oxide layer are sequentially formed on a substrate. The top oxide layer, the nitride layer and the bottom oxide layer are then patterned to form a composite gate dielectric. Ions are implanted into the substrate by using the composite gate dielectric as a mask to form source/drains in the substrate on the two sides of the composite gate dielectric. A conformal oxide layer is deposited on surfaces of the composite gate dielectric and the source/drains by chemical vapor deposition. Surfaces of the substrate uncovered by the composite gate dielectric are thermally oxidized to form bit line oxides. A conductive layer is formed on the substrate and then patterned to form a gate over the composite gate dielectric and the bit line oxides.
In the foregoing, the conformal oxide layer is preferably a high-temperature-oxide layer formed by low-pressure vapor deposition.
In conclusion, the invention utilizes chemical vapor deposition to deposit the conformal oxide layer, which covers the exposed surface of the composite gate dielectric. Therefore, the surface of the nitride layer in the composite gate dielectric does not directly contact the gate, which would cause current leakage. Consequently, the retention time of charges stored in the nitride layer can be increased, and the thermal budget of the fabricating process and the lateral diffusion of the source/drains can be decreased.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5966603 (1999-10-01), Eitan
patent: 6218227 (2001-04-01), Park et al.
patent: 6297096 (2001-10-01), Boaz
patent: 6319775 (2001-11-01), Halliyal et al.

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