Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-27
2003-10-07
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S765010
Reexamination Certificate
active
06631486
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to an improved semiconductor integrated circuit operating at a high speed, and more particularly relates to a semiconductor integrated circuit that is testable by a tester operating at a speed lower than the operating speed of the integrated circuit.
Over the past few years, ultra-high-speed interfaces are under vigorous research and development, thereby tremendously speeding up the operation of an LSI. For example, according to the IEEE 1394 standard, it is now possible to present image data, which has been transmitted at a high transfer rate, on a display. In contrast, testers intended to test those high-speed-operating LSI's have not been developed so rapidly as the LSI's themselves up to now.
A conventional high-speed-LSI tester includes a data generator for generating data at a frequency approximately as high as the operating speed of an LSI under the test. The tester further includes a high-transfer-rate comparator for comparing a high-transfer-rate signal, which has been obtained as a result of testing the high-speed LSI and transferred at a high rate, to an expected value thereof. In performing a high-transfer-rate data transmission test on a device operating at a high speed, a low-transfer-rate data with a predetermined test pattern is generated by the data generator within the tester and input to the device under the test. Thereafter, the frequency of the input data is divided using a phase-locked loop (PLL) within a logic circuit included in the device under the test, thereby converting the low-transfer-rate input data into high-transfer-rate data. Then, the resultant high-transfer-rate data is transmitted from a high-speed. transmitter, which is included in the device under the test, to the tester. And the tester gets the received high-transfer-rate data compared by the high-transfer-rate comparator to the expected value thereof. In performing a high-transfer-rate data reception test on the other hand, high-transfer-rate data is transmitted from the data generator within the tester to the device under the test. In the device under the test, the high-transfer-rate data is received by a high-speed receiver, and then the frequency of the high-transfer-rate data is divided by an internal logic circuit, thereby converting the high-transfer-rate data into low-transfer-rate data. And then the tester gets the received low-transfer-rate data compared by the comparator to the expected value thereof.
FIG. 7
illustrates how a high-speed device is tested using a conventional tester. In the illustrated example, a high-speed-LSI tester J971 (manufactured by Teradyne Corp., USA) may be used. In performing a high-transfer-rate data transmission test on a device
70
under the test (DUT), i.e., if the DUT
70
requires a high-rate transfer, an input test pattern with an ordinary transfer rate of 50 Mbps, for example, is generated by a data generator
61
in a tester
60
and input to the DUT
70
. The input pattern is received by a first logic circuit
71
in the DUT
70
. Thereafter, the frequency of the input pattern is divided using a PLL (not shown), for example, within the first logic circuit
71
, thereby converting the input pattern into a pattern signal with a transfer rate as high as 400 Mbps, for example. Then, the resultant high-transfer-rate pattern signal is transmitted from a high-speed a transmitter
72
to the tester
60
. And the tester
60
gets the received high-transfer-rate pattern signal compared by a high-transfer-rate comparator
62
to an expected pattern thereof supplied from the data generator
61
.
In performing a high-transfer-rate data reception test on the other hand, a high-transfer-rate data generator
63
included in the tester
60
outputs a high-transfer-rate pattern signal to the DUT
70
at a transfer rate as high as the data transfer rate (e.g., 400 Mbps) of the DUT
70
. In the DUT
70
, the high-transfer-rate pattern signal is received by a high-speed receiver
73
, and then the frequency of the high-transfer-rate pattern signal is divided by a second logic circuit
74
, thereby converting the high-transfer-rate pattern signal into a low-transfer-rate pattern signal with an ordinary transfer rate (e.g., 50 Mbps). And then the tester
60
gets the received low-transfer-rate pattern signal compared by a comparator
64
to the expected value thereof.
Accordingly, the conventional tester
60
needs to include the high-transfer-rate comparator
62
for the high-transfer-rate data transmission test and the high-transfer-rate data generator
63
for the high-transfer-rate data reception test.
The high-transfer-rate comparator
62
and high-transfer-rate data generator
63
of the tester
60
, however, are both very expensive. Thus, the test cost adversely increases with these components.
In addition, since semiconductor integrated circuits have been further modified to operate at increasingly high speeds in recent years, such an LSI tester cannot satisfactorily catch up with the latest trend in the art. Also, even if the testers could catch up with the semiconductor integrated circuits increasing their speeds day after day, it would take enormous costs to develop a brand-new tester operating as fast as the state-of-the-art semiconductor integrated circuit every time the integrated circuit has increased its speed. Furthermore, even if a brand-new LSI tester is developed by a maker every time an LSI has increased it speed, older LSI testers manufactured by the other makers will also be used. In such a situation, it would take a long time to convert programs.
Moreover, once a device under test has increased its operating speed, skewing of a transferred signal and/or a voltage drop thereof caused during the propagation through interconnection lines should also be tested. The conventional tester can control the delay or voltage drop, and therefore, the worst-case skew can be tested as for a signal to be received by the device under the test. However, the worst-case signal skewing or voltage drop, which has been caused in the device under the test itself, cannot be tested.
SUMMARY OF THE INVENTION
An object of the present invention is providing a semiconductor integrated circuit that is testable by an ordinary tester applicable to low-transfer-rate signals.
Another object of the present invention is providing a method for testing a semiconductor integrated circuit with respect to the worst-case voltage drop and skewing, which might happen in the integrated circuit while a high-transfer-rate signal is being transmitted, by intentionally causing that voltage drop and skewing in the circuit.
To achieve these objects, according to the present invention, a high-transfer-rate signal, which has been transmitted from a transmitter in a semiconductor integrated circuit, is received by a receiver within the same circuit and then converted into a low-transfer-rate signal to be sent back to, and tested by, a tester.
In addition, according to the present invention, a potential controller for getting the potential of the high-transfer-rate signal dropped and a delay circuit for causing a compulsory skew between two signals included in a high-transfer-rate differential signal are provided for the semiconductor integrated circuit under the test.
A semiconductor integrated circuit of the present invention includes a transmitter for transmitting a high-transfer-rate signal and a receiver. The integrated circuit is characterized by further including: a first logic circuit for receiving a low-transfer-rate signal from an external tester, generating the high-transfer-rate signal responsive to the low-transfer-rate signal and outputting the high-transfer-rate signal to the transmitter while the integrated circuit is connected to the external tester to carry out a test; a signal line coupling the transmitter and receiver together; switching means, which is provided for the signal line and is turned ON during the test to transmit the high-transfer-rate signal from the transmitter to the receiver; and
Arima Yukio
Komatsu Yoshihide
Yoshida Tadahiro
De'cady Albert
Lamarre Guy
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
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