Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-01-17
2003-12-09
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S689000, C438S710000, C438S712000, C438S719000, C438S720000, C438S723000, C438S725000, C438S733000, C438S740000, C438S789000, C438S769000, C438S780000, C438S637000
Reexamination Certificate
active
06660645
ABSTRACT:
FIELD OF THE INVENTION
Embodiments of the present invention pertain to semiconductor fabrication, and in particular to processes for etching a feature in a low dielectric constant (low-k) organic dielectric.
BACKGROUND TECHNOLOGY
Integrated circuits(ICs) are manufactured by forming discrete semiconductor devices on the surface of a silicon wafer, and then forming a metal interconnection network in contact with the devices to create circuits. The metal interconnection network is composed of horizontal layers of individual metal wirings that are interconnected by vertical contacts or vias. Contacts and vias are formed by depositing an insulating layer over a structure to be contacted, such as a discrete device or a metal wiring, patterning and etching openings into the insulating layer, and then depositing metal into the openings in contact with the underlying device or wiring. Wiring may be formed by applying a metal layer over an insulating layer, patterning the metal layer into individual metal wires, and applying an interlevel dielectric material to fill the spaces between the wires. Alternatively, metal wiring may be formed using a damascene technique by depositing an insulating layer, forming trenches in the insulating layer, depositing metal over the insulating layer, and polishing back the metal to the surface of the insulating layer, leaving trenches filled with metal. A typical interconnection network employs multiple levels of wiring and vias.
The performance of integrated circuits is determined in large part by the conductance and capacitance of the metal wiring network. Conventionally, aluminum wiring and silicon oxide interlevel dielectric layers have been used. However, as device densities increase and geometries decrease, the RC time constraints of the interconnection network have increasingly restricted integrated circuit performance. To address this problem, various low dielectric constant organic insulators such as parylene and arylene ether polymers have been employed successfully as replacements for silicon oxide. Examples of such polymers are disclosed in U.S. Pat. No. 5,115,082 and U.S. Pat. No. 5,658,994. The term “low-k,” when applied to organic dielectrics generally refers to a dielectric constant of less than about 3.5 and preferably less than about 2. For example, the conventional organic low-k dielectrics known as PAE-2 and PAE-4, have dielectric constants of 2.41 and 2.42 respectively when measured at 1 MHz. Organic low-k dielectrics are typically spin coated onto silicon wafers and cured.
Many conventional dielectric patterning processes utilize a photoresist mask as an etch mask in a plasma etching or reactive ion etching (RIE) process. However, where organic low-k dielectric materials are used, the use of photoresist etch mask is problematic because the O
2
/Ar or O
2
/He etchant chemistry that is conventionally employed to etch the organic dielectric has a low selectivity with respect to photoresist. Conventional techniques address this problem by employing a hardmask to etch the organic dielectric. Typically, a layer of silicon oxide, deposited by PECVD (plasma enhanced chemical vapor deposition) is applied over the cured organic dielectric. A silicon oxide hardmask is formed by patterning the silicon oxide layer. The silicon oxide hardmask is then used to pattern the underlying organic dielectric. However this process has several complications. Stripping of the photoresist mask from the hardmask entails selectivity problems with respect to the organic dielectric. Further, the chemistry used to etch the organic dielectric creates problems with respect to the profile of the opening in the hardmask and the sidewall profile of the etched organic dielectric. The etching conditions that produce straight sidewalls in the organic dielectric etch the sidewalls of the openings in the hardmask such that they become angled and broader at their tops. This condition, referred to as faceting, degrades pattern integrity and can cause a high incidence of via shorts. It would therefore be advantageous to remove the faceted hardmask after etching of the organic layer. However, the chemistry for removing the hardmask is damaging to the conductive layer that is exposed by etching the organic layer. Thus it is desirable to adjust the etching conditions to eliminate faceting. However, the etching conditions that prevent faceting produce a bowed profile in the sidewalls of the organic dielectric. Consequently, conventional hardmask techniques represent a compromise between these two undesirable effects that is unable to completely avoid either of bowed sidewalls and faceted hardmask.
Conventional integrated circuit fabrication techniques may employ a process known as silyation. Generally, silyation involves the introduction of silicon into a photoresist material. Conventional techniques use silyation in combination with projection lithography in a process called a dual multilayer resist process. In this process, a thick layer of photoresist is applied over a non-uniform substrate to provide a planar photoresist surface. A pattern is then projected onto the photoresist, causing exposure of an upper portion of the photoresist layer. This is referred to as top surface imaging (TSI). Depending on the photoresist chemistry, the exposure increases or decreases the permeability of the photoresist to silicon in the exposed area. A silyation process is then performed to selectively introduce silicon into the permeable areas of the photoresist. The photoresist is then exposed to an anisotropic oxygen plasma etch, which converts the silyated photoresist to etch resistant silicon dioxide while simultaneously etching the photoresist that does not lie beneath the silyated photoresist areas. This technique allows the formation of a planar surface through application of a thick layer of photoresist to avoid distortions that would be caused by projection onto a nonplanar layer, without introducing the optical distortions that would result from exposure of the entire thickness of the photoresist.
Various chemistries for silyation of photoresist are known in the art. Silyation agents may be supplied as a gas in a dry silyation method, such as is described in U.S. Pat. No. 5,562,801, or may be supplied as a liquid in a wet chemistry method, such as is described in U.S. Pat. No. 6,063,543.
While silyation has been used to minimize defects in patterns formed in a photoresist layer by projection lithography, conventional technology has not employed silyation for the purpose of resolving the etch selectivity problem between photoresist and organic low-k dielectric.
Thus there remains a need for a process that allows a photoresist mask to be employed as an etch mask for an organic low-k dielectric while avoiding etch selectivity problems.
SUMMARY OF THE INVENTION
In accordance with embodiments of the invention, a photoresist mask may be employed as an etch mask for an organic low-k dielectric. The photoresist mask is silyated prior to etching, thereby increasing its resistance to the etching chemistry used to etch the organic low-k dielectric. The O
2
plasma etch of the organic low-k dielectric further converts the silyated photoresist to silicon oxide. Thus, stripping of the silyated photoresist mask may be performed using an etch chemistry that is selective to silicon oxide and does not etch the sidewalls of the organic low-k dielectric.
In accordance with embodiments of the invention, a process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.
REFERENCES:
patent: 5115082 (1992-05-01), Mercer et al.
patent
Bell Scott A.
Lukanc Todd P.
Lyons Christopher F.
Plat Marina V.
Subramanian Ramkumar
Advanced Micro Devices , Inc.
Cuneo Kamand
Foley & Lardner
Kilday Lisa
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