Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-03
2003-06-10
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S211000, C438S257000
Reexamination Certificate
active
06576514
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of forming a polysilicon layer on a semiconductor wafer, and more particularly, to a method of forming a three-dimensional polysilicon layer on a semiconductor wafer.
2. Description of the Prior Art
In semiconductor application, a non-volatile memory such as an erasable and programmable read only memory (EPROM), electrically erasable programmable read only memory (E
2
PROM) and flash memory all store data in the memory whether an electrical power is supplied or not, and read and write data through controlling a threshold voltage of a control gate. The structure of the non-volatile memory is designed as a stack-gate. The stack-gate comprises a floating gate for storing charge, an ONO (oxide-nitride-oxide) dielectric layer and a control gate for reading and writing of the data. Like a capacitor storing data, the memory store charge in the stack-gate for representing the data “1” and erase the charge from the stack-gate for representing the data “0”. Additionally, the data storing in the memory is renewed through applying an extra energy to the stack-gate.
Please refer to
FIG. 1
to FIG.
4
.
FIG. 1
to
FIG. 4
are cross-sectional diagrams of forming a stack-gate
36
according to the prior art. The method of forming the stack-gate
36
on a semiconductor wafer
10
is forming a twin cell gate on the semiconductor wafer
10
. The semiconductor wafer
10
comprises a silicon substrate
12
, two field oxide
14
positioned on the substrate
12
, two gate oxide layer
16
positioned in a predetermined area between the field oxide
14
, two polysilicon layer
18
positioned on the gate oxide layer
16
and two silicon nitride layer
20
positioned on the polysilicon layer
18
, as shown in FIG.
1
.
According to the prior art, an ion implantation process is performed to implant ion on the surface of the substrate
12
that is not covered by the gate oxide layer
16
and the field oxide
14
. A thermal oxidation process is then performed to diffuse the ion into a predetermined depth and form three ion implantation layer
22
serving as a buried drain or a source. The thermal oxidation process also grows a thermal oxide layer
24
on the ion implantation layer
22
to form a buried drain and a buried source (BD/BS) on the surface of the substrate
12
, as show in FIG.
2
. The silicon nitride layer
20
is then totally removed and two polysilicon layer
26
are formed in a predetermined area on the surface of the semiconductor wafer
10
. Each polysilicon layer
18
together with the polysilicon layer
26
on the polysilicon layer
18
form a three-dimensional polysilicon layer
28
serving as a floating gate of a non-volatile memory, as shown in FIG.
3
.
Please refer to
FIG. 4. A
dielectric layer
30
is formed on the surface of the floating gate and a polysilicon layer
32
is then formed on the surface of the semiconductor wafer
10
. The polysilicon layer
32
serves as a control gate of the stack-gate and covers the surface of both the dielectric layer
30
and the thermal oxide layer
24
. The dielectric layer
30
is an ONO structure that comprises a native oxide as a first oxide layer, a nitride layer positioned on the first oxide layer and a second oxide layer positioned on the nitride layer.
The floating gate, the dielectric layer
30
and the control gate together constitute the stack-gate
36
of the non-volatile memory. The two stack-gates
36
between the filed oxide
14
form the twin cell gate. When a high voltage is applied on the control gate of the stack-gate, the drain generates hot electrons due to the carrier multiplication. Some of the hot electrons transverse through the gate oxide layer
16
into the floating gate. The floating gate is charged and the data is written into the stack-gate. Because the dielectric layer
30
and the gate oxide layer
16
are insulated, the charge provided by the hot electrons is trapped in the floating gate.
According to the prior art, the thermal oxide layer
24
, that serves as the BD/BS, is formed on the surface of the substrate
12
by performing a thermal oxidation process. Because the restriction of the field oxide
14
, the thickness of the thermal oxide layer
24
is not uniform, the thermal oxide layer
24
forms a bird peak, the lattice structure of the substrate
12
is damaged, and the reliability of the stack-gate
36
is dramatically reduced. Additionally, because the thermal oxidation process overly diffuses the ion in the drain and source, the channel length under the stack-gate
36
is relatively shorten. This causes an occurrence of a punch through between the source and the drain, influences the electrical performance of the stack-gate
36
and reduces the yield rate of the semiconductor product.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a three-dimensional polysilicon layer to construct a stack-gate of a non-volatile memory.
According to the claimed invention, a semiconductor wafer is provided, the semiconductor wafer including a substrate, a first polysilicon layer having an approximately rectangular cross-section positioned on the substrate, and a sacrificial layer positioned on the first polysilicon layer. A dielectric layer is formed to cover the substrate and the sacrificial layer. A portion of the dielectric layer is removed to expose an upper portion of the sidewalls of the sacrificial layer. Following this, a passivation layer is formed on the surface of the dielectric layer and contacts the exposed sidewalls of the upper portion of the sacrificial layer. Then, both the passivation layer and the dielectric layer positioned over the sacrificial layer are removed down to a predetermined height by CMP. The dielectric layer is removed from the sacrificial layer followed by removing the passivation layer from the surface of the semiconductor wafer and removing the sacrificial layer from the first polysilicon layer. As a result, a recess is formed using the first polysilicon layer as the bottom of the recess and using the remaining dielectric layer as the walls of the recess. Finally, a second polysilicon layer is formed on the semiconductor wafer to form a floating gate. Since the surface of the second polysilicon layer follows the shape of the recess to form a three-dimensional structure, a contact area between an ONO dielectric layer and a control gate forming on the floating gate in a later process is increased to raise the coupling ratio of the floating gate.
It is an advantage of the present invention that a stack-gate, composing of the floating gate, the ONO dielectric layer and the control gate, has three-dimensional structure, to increase the contact area between the ONO dielectric layer and the control gate and thus raise the gate coupling ration of the stack-gate to 60~75%. Additionally, the passivation layer is formed on the surface of the dielectric layer to ensure the thickness of the dielectric layer around the first polysilicon layer and the channel length of the stack-gate being controlled. Thus, the size of the devices is effectively shrunk and the reliability of the devices is greatly improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
REFERENCES:
patent: 6248631 (2001-06-01), Huang et al.
patent: 6458660 (2002-10-01), Chang et al.
Huang Chin-Yi
Huang Weng-Hsing
Liu Chen-Chin
Fourson George
Hsu Winston
Macronix International Co. Ltd.
Pham Thanh V
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