Non-volatile memory cell having bilayered floating gate and...

Details Non-volatile memory cell having bilayered floating gate and... Non-volatile memory cell having bilayered floating gate and...

2001-02-22

2003-12-30

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C438S593000

Reexamination Certificate

active

06670239

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory cell and a method for manufacturing the same, and more particularly, to a non-volatile memory cell having a bilayered floating gate and a method for manufacturing the same.
2. Description of the Related Art
In general, a memory cell having a structure in which a floating gate and a control gate are sequentially stacked is widely used as a unit cell of a non-volatile memory. The floating gate stores data and the control gate controls the floating gate. An interlayer dielectric layer is interposed between the floating gate and the control gate.
FIG. 1
is a layout diagram showing an example of a conventional non-volatile memory cell.
FIG. 2
is a sectional view taken along the line A-A′ of FIG.
1
. Referring to
FIGS. 1 and 2
, buried N
+
source/drain regions
13
are vertically formed in stripe fashion in a semiconductor substrate
10
. Second polysilicon layer patterns
16
used as control gate electrodes are horizontally formed in stripe fashion crossing the buried N
+
source/drain regions
13
. In a region where the second polysilicon layer patterns
16
exist, tunnel oxide layers
11
, first polysilicon layer patterns
12
used as floating gate electrodes, field oxide layers
14
, and interlayer dielectric layers
15
are sequentially formed between the substrate
10
and the second polysilicon layer patterns
16
(refer to FIG.
2
).
A smaller number of contacts can be used for the conventional non-volatile memory cell having such a structure. Also, it is possible to improve the density of a device since the field oxide layers
14
are formed on the semiconductor substrate
10
. However, since the interlayer dielectric layers
15
are formed only on the upper surfaces of the first polysilicon layer patterns
12
, the coupling ratio of the floating gate is low. Since the coupling ratio of the floating gate is low, it is difficult to minimize the width of the second polysilicon layer patterns
16
. Accordingly, there are limitations in improving the density of such devices. Furthermore, during manufacturing processes, first polysilicon stringers can remain between the first polysilicon layer patterns
12
during an etching process for forming the second polysilicon layer patterns
16
, the interlayer dielectric layers
15
, and the first polysilicon layer patterns
12
. Therefor, the reliability of a device can deteriorate.
SUMMARY OF THE INVENTION
To solve the above problem, it is an object of the present invention to provide a non-volatile memory cell having a bilayered floating gate, capable of maintaining a high density and increasing the coupling ratio of a floating gate.
It is another object of the present invention to provide a method for manufacturing a non-volatile memory cell having the bilayered floating gate, capable of solving various problems during an etching process.
Accordingly, in accordance with the invention, there is provided a non-volatile memory cell which includes a first conductivity type semiconductor substrate, and second conductivity type source/drain regions longitudinally arranged in a direction to be parallel to each other and separated from each other by a predetermined distance in the semiconductor substrate. The second conductivity type source/drain regions define a channel region therebetween. A tunnel oxide layer is formed on the semiconductor substrate. First conductive layer patterns are formed on the tunnel oxide layer on the channel formation region in the form of islands. Buried oxide layers filling spaces between adjacent first conductive layer patterns. Second conductive layer patterns are formed on the upper surfaces and the upper side surfaces of the first conductive layer patterns and are arranged so that their edges are extended to some surfaces of the buried oxide layers. An interlayer dielectric layer is formed on the second conductive layer patterns, and third conductive layer patterns are arranged to be vertical to the source/drain regions on the interlayer dielectric layer patterns.
The first conductive layer patterns and the second conductive layer patterns can operate as floating gates and the third conductive layer patterns can operate as control gates.
In one embodiment, the thickness of the tunnel oxide layer is about 90 to 100 Å, and the thickness of the first conductive layer pattern is preferably no less than 1000 Å.
In one embodiment, the first, second, and third conductive layer patterns are formed of polysilicon doped with impurities.
The buried oxide layer can be a flowable oxide layer.
The thickness of the buried oxide layer is preferably smaller than the thickness of the first conductive layer pattern. A difference between the thickness of the buried oxide layer and the thickness of the first conductive layer pattern is preferably about 20 Å.
The non-volatile memory cell can further comprise a first conductive isolation region located on the semiconductor substrate and formed between the adjacent first conductive layer patterns along the direction of the source/drain region.
In one embodiment, the first conductivity type is P type and the second conductivity type is N type.
In another aspect, the invention is directed to a method for forming a non-volatile memory cell. In accordance with the method, a tunnel oxide layer is formed on a first conductivity type semiconductor substrate. First polysilicon layer lines longitudinally arranged in a bit line direction and separated from each other by a predetermined direction are formed on the tunnel oxide layer. Source and drain regions are formed by implanting second conductivity type impurity ions in the semiconductor substrate restricted by the first polysilicon layer lines. First polysilicon layer patterns in the form of islands are formed by patterning the first polysilicon layer lines. Buried oxide layers for filling spaces between the first polysilicon layer patterns are formed. Second polysilicon layer lines longitudinally arranged in the bit line direction are formed to be separated from each other on the buried oxide layers and the first polysilicon layer patterns so that the second polysilicon layer lines completely cover the first polysilicon layer patterns. An interlayer dielectric layer is formed on the exposed surfaces of the second polysilicon layer lines and the buried oxide layers. Third polysilicon layer patterns longitudinally arranged in a word line direction are formed on the interlayer dielectric layer so that the third polysilicon layer patterns completely overlap the first polysilicon layer patterns and partially overlap the second polysilicon layer lines. The interlayer dielectric layer and the second polysilicon layer lines, which are exposed by the third polysilicon layer patterns, are sequentially removed.
In one embodiment, the first polysilicon layer lines are formed to have a thickness greater than 1000 Å.
The second conductivity type impurity ions can be arsenic (As) ions.
The buried oxide layers can be formed by a chemical vapor deposition (CVD) method.
Forming the buried oxide layers can include forming an oxide layer on the first polysilicon layer patterns and the exposed tunnel oxide layer and flattening the oxide layer using an etch back process so that the upper side surfaces of the first polysilicon layer patterns are exposed.
In one embodiment, the thickness of the buried oxide layer is smaller than the thickness of the first polysilicon layer patterns by 20 Å.
The interlayer dielectric layer can be formed to have an oxide
itride/oxide (ONO) structure.


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